R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 60

• Manufacturer Part Number: R0K561668S000BE
• Description: KIT STARTER FOR H8SX/1668
• Manufacturer: Renesas Electronics America
• Series: H8®r
• Type: MCUr

Specifications of R0K561668S000BE

• For Use With/related Products: H8SX/1668
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Section 1 CPU
value should be an even number. In advanced mode, only the lower 24 bits of this branch address
are valid; the upper 8 bits are all assumed to be 0 (H'00).
1.8.9
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,
which is the sum of the following operation result and the 32-bit address of the PC contents: the
contents of an address register specified by the register field in the instruction code (RnL, Rn, or
ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is
the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of
this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).
1.8.10
This mode can be used by the JMP and JSR instructions. The operand value is a branch address,
which is the contents of a memory location pointed to by an 8-bit absolute address in the
instruction code.
The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes).
In normal mode, the memory location is pointed to by word-size data and the branch address is 16
bits long. In other modes, the memory location is pointed to by longword-size data. In middle or
advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).
Note that the top part of the address range is also used as the exception handling vector area. A
vector address of an exception handling other than a reset or a CPU address error can be changed
by VBR.
Figure 1.15 shows an example of specification of a branch address using this addressing mode.
Rev. 4.00 Sep. 18, 2008 Page 42 of 914
REJ09B0102-0400
@(ERn.L, PC)
Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC), or
Memory Indirect—@@aa:8