R0K561668S000BE Renesas Electronics America, R0K561668S000BE Datasheet - Page 652
R0K561668S000BE
Manufacturer Part Number
R0K561668S000BE
Description
KIT STARTER FOR H8SX/1668
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Specifications of R0K561668S000BE
For Use With/related Products
H8SX/1668
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Contents
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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System control (4)
Notes:
Instructio
n
RTE/L
Mnemonic
RTE/L (ERn-ERn+2)
RTE/L (ERn-ERn+3)
1.
2.
3.
4.
5.
6.
Values given in the table above are number of states for execution when the following conditions hold.
Number of states for execution can change according to the conditions of instruction execution.
In addition, the number of states may be reduced depending on the product.
(1) The values of the MOVSD instruction are the values when zero data has not been detected. The values of other conditional instructions are when
(2) It is assumed that word data is located to an even address and longword data is located to an address which is a multiple of 4.
(3) It is assumed that stacking in exception handling is performed when EXR is invalid in normal mode.
(4) It is assumed that a stall caused by a resource conflict is not occurred.
For details on changes in the condition code, see section 2.5, Condition Code Modification.
When EXR is valid or in maximum mode.
@ERn+ for a source and @-ERn for a destination.
ER5 for a source address of data transfer and ER6 for a destination address.
When using the same general register for the source operand and destination operand in the register indirect addressing mode with pre-/post-increment or
pre-/post-decrement, see section 1.8.5, Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement@ERn+, @−ERn,
@+ERn, or @ERn−.
conditions are satisfied.
L 1 7 7
L 1 8 8
Addressing Mode
O @SP+→ERn+2
O @SP+→ERn+3
Operation 1
@SP+→ERn+1
@SP+→ERn
@SP+→ERn+2
@SP+→ERn+1
@SP+→ERn
Operation 2
@SP+→EXR*
@SP+→CCR
@SP+→EXR*
@SP+→CCR
3
3
Operation 3
@SP+
@SP+
Operation*
6
→ PC
→ PC
Operation 4
Operation 5
I
Condition Code*
H
N
Z
V
2
C
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