DK-VIDEO-4SGX230N Altera, DK-VIDEO-4SGX230N Datasheet - Page 27

• Manufacturer Part Number: DK-VIDEO-4SGX230N
• Description: VIDEO KIT STRATIX IV EP4SGX230
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-VIDEO-4SGX230N

• Contents: Board, Daughter Card, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2602

Chapter 6: Board Test System
Using the Board Test System
© November 2009 Altera Corporation
1
1
Table 6–1. MAX II Registers
■
■
■
■
Because the Config tab requires that a specific design is running in the FPGA, writing
a 0 to SRST or changing the PSO value can cause the Board Test System to stop
running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The Stratix
IV GX device is always the first device in the chain.
Setting DIP switch SW6.1 to the off position includes the MAX II device in the JTAG
chain.
Board Information
The Board information controls display static information about your board.
■
System Reset
(SRST)
Page Select Register
(PSR)
Page Select Override
(PSO)
Page Select Switch
(PSS)
Register Name
PSO—Sets the MAX II PSO register. The following options are available:
■
■
PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to
for more information.
PSS—Displays the MAX II PSS register value. Refer to
available options.
SRST—Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to
MAX II ver—Indicates the version of MAX II code currently running on the board.
The MAX II code resides in the <install
dir>\kits\stratixIVGX_4sgx230_av\examples directory. Newer revisions of this
code might be available on the
Edition
Use PSR—Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
Use PSS—Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
page of the Altera website.
Write only
Read / Write
Read / Write
Read only
Read/Write
Capability
Set to 0 to initiate an FPGA reconfiguration.
Determines which of the up to eight (0-7) pages of flash
memory to use for FPGA reconfiguration. The flash memory
ships with pages 0 and 1 preconfigured.
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Holds the current value of the rotary switch (SW2).
Audio Video Development Kit, Stratix IV GX
Audio Video Development Kit, Stratix IV GX Edition User Guide
Table 6–1
Description
Table 6–1
for more information.
for the list of
Table 6–1
6–5