DK-VIDEO-4SGX230N Altera, DK-VIDEO-4SGX230N Datasheet - Page 44

• Manufacturer Part Number: DK-VIDEO-4SGX230N
• Description: VIDEO KIT STRATIX IV EP4SGX230
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-VIDEO-4SGX230N

• Contents: Board, Daughter Card, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2602

6–22
The Power Monitor
Audio Video Development Kit, Stratix IV GX Edition User Guide
1
■
■
■
Receiver Status
These controls show the settings for each receiver channel on the SDI HSMC. Both
receiver channels (CH1 RX and CH2 RX) operate independently but must have the
same clock source or be synchronized with each other.
■
The Power Monitor measures and reports current power and temperature
information for the board. To start the application, click Power Monitor in the Board
Test System application.
You can also run the Power Monitor as a stand-alone application. PowerMonitor.exe
resides in the <install
dir>\kits\stratixIVGX_4sgx230_av\examples\board_test_system directory. On
Windows, click Start > All Programs > Altera > Audio Video Development Kit,
Stratix IV GX Edition <version> > Power Monitor to start the application.
The Power Monitor communicates with the MAX II device on the board through the
JTAG bus. A power monitor circuit attached to the MAX II device allows you to
measure the power that the Stratix IV GX FPGA device is consuming regardless of the
design currently running.
Clock source—Specifies the clock the SDI HSMC PLL locks to. The following
choices are available:
■
■
Intensity—Specifies the color intensity of the transmitted color bar pattern.
SDI standard—Specifies the video standard the pattern generator uses on the SDI
video stream. The following choices are available:
■
■
■
CH1 Rx status and CH2 Rx status—Show the status of the following receiver
channel attributes:
■
■
■
■
Lock to host—Locks the SDI HSMC PLL to the local reference on the Stratix IV
GX FPGA development board.
Lock to input—Locks the SDI HSMC PLL to the SDI input stream.
SD—Specifies a 270 Mbps data rate
HD—Specifies a 1.485 Gbps data rate
3G HD—Specifies a 2.97 Gbps data rate
Alignment—Shows the alignment locked or unlocked state. "Locked" indicates
that the TRS pattern has been received and data is word aligned.
TRS—Shows the TRS locked or unlocked state. "Locked" indicates the six TRS
patterns have been received with the same timing.
Frame—Shows the frame locked or unlocked state. "Locked" indicates the
frame sync patterns have been received.
Standard—Shows the type of video input (SD, HD, or 3G) the channel is
receiving.
Figure 6–12
shows the Power Monitor.
© November 2009 Altera Corporation
Chapter 6: Board Test System
The Power Monitor