STV-974/552S-R01 STMicroelectronics, STV-974/552S-R01 Datasheet - Page 26

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STV-974/552S-R01

Manufacturer Part Number
STV-974/552S-R01
Description
KIT DEMO W/VS6552
Manufacturer
STMicroelectronics

Specifications of STV-974/552S-R01

Sensor Type
CMOS Imaging, Color (RGB)
Sensing Range
VGA
Interface
I²C
Sensitivity
30 fps
Embedded
No
Utilized Ic / Part
STV0974E, VS6552
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-3891
STV0974
4.5.5
FIFO Count Register (FCNT)
FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO.
Table 20: FIFO Count Register
Image transfer operation
Interrupt controlled transfer
The STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs
the following operations:
1 Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and
2 Acknowledge pending interrupts by writing ICLR.
3 Service the interrupt source(s), i.e. for example:
4 Interrupts can be disabled through IMASK.
DMA controlled transfer
The STV0974 supports DMA operation for image data transfer: the DRQ output signal is used to
trigger a DMA burst read transfer from peripheral to memory. A full image transfer under DMA
executes as follows:
Figure 12: Full image transfer under DMA
1 The STV0974 is initialized: DMA burst size, FIFO is cleared.
2 DRQ is asserted when the image FIFO threshold is reached or exceeded.
3 The DMA controller starts performing the burst read transfer consisting of 8, 16 or 32 byte reads.
[15:0]
Bits
detect the active interrupt sources.
MCI: read micro-core status and error registers (camera control channel).
SOF: trigger frame synchronous task.
FF: empty the FIFO by reading 16-byte blocks (camera image data channel).
RDY: read DR for a pending read, write next AR (low-level byte transfer).
FCNT
Name
FIFO level
threshold
(POL = 0)
Frame
Read
FIFO
DRQ
IRQ
RO
Type
Number of bytes available in the image data FIFO.
1 2
1
n
Description
1
n
Functional description
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