STV-974/552S-R01 STMicroelectronics, STV-974/552S-R01 Datasheet - Page 24

• Manufacturer Part Number: STV-974/552S-R01
• Description: KIT DEMO W/VS6552
• Manufacturer: STMicroelectronics

Specifications of STV-974/552S-R01

• Sensor Type: CMOS Imaging, Color (RGB)
• Sensing Range: VGA
• Interface: I²C
• Sensitivity: 30 fps
• Embedded: No
• Utilized Ic / Part: STV0974E, VS6552
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3891

STV0974
FIFO Register (FIFO)
FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data
FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the
threshold. Reading from an empty FIFO returns the last valid byte read.
The image data FIFO is cleared at the beginning of VENV, the image vertical envelope. If the FIFO
is not empty, its contents are discarded and the FERR flag is raised in the status register SR. New
image data start to fill in the FIFO. If an overflow occurs during VENV, the FERR flag is also raised
in SR; FERR can be cleared through ICLR.
Table 14: FIFO register
Microprocessor Interface Control Register (MICR)
MICR controls and configures the image data transfer.
Table 15: Microprocessor Interface Control Register
[7:0]
[7:6]
5
4
[3:2]
1
0
Bits
Bits
FIFO
-
IRQPOL
DRQPOL
BSIZE
-
CLR
Name
Name
RO
Type
-
RW
RW
RW
-
WO
Type
Image data byte (uncompressed or compressed).
Reserved.
IRQ pin polarity:
0 = active high
1 = active low
DRQ pin polarity:
0 = active high
1 = active low
DMA burst size and enable:
00 = DMA operation disabled, DRQ pin is high impedance
01 = 8-byte burst
10 = 16-byte burst
11 = 32-byte burst
Reserved, read as zero, ignored upon write
Clear FIFO (Write Only, read as 0):
0 = No action
1 = Reset FIFO to empty state
Description
Description
Functional description
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