STV-974/552S-R01 STMicroelectronics, STV-974/552S-R01 Datasheet - Page 22

• Manufacturer Part Number: STV-974/552S-R01
• Description: KIT DEMO W/VS6552
• Manufacturer: STMicroelectronics

Specifications of STV-974/552S-R01

• Sensor Type: CMOS Imaging, Color (RGB)
• Sensing Range: VGA
• Interface: I²C
• Sensitivity: 30 fps
• Embedded: No
• Utilized Ic / Part: STV0974E, VS6552
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-3891

STV0974
Status Register (SR)
The status register is an 8-bit read-only direct register holding all pending requests from the camera
subsystem.
Table 10: Status Register
7
6
5
4
3
2
1
0
Bits
IRQ
-
EOF
SOF
MCI
FERR
FRDY
RDY
Name
RO
-
-
RO
RO
RO
RO
RO
Type
Interrupt Request: IRQ is set when at least one of the interrupt sources is set, and the
corresponding bit mask is set.
Reserved.
End Of Frame: EOF is set by the falling edge of VENV
(output image vertical envelope).
SOF is cleared by writing ICLR bit 5.
Start Of Frame: SOF is set by the rising edge of VENV (output image vertical
envelope).
SOF is cleared by writing ICLR bit 4.
Micro-Core Interrupt: MCI is set by the micro-core to alert the host of the occurrence
of an internal event (status update, error, etc.…).
MCI is cleared by writing ICLR bit 3.
FIFO Error: FERR is set by the FIFO controller if a FIFO overflow occurs, or if the
FIFO is not empty when cleared at the start of frame.
FERR is cleared by writing ICLR bit 2.
FIFO Ready: This bit indicates that the number of valid bytes in the FIFO is greater
than or equal to the FIFO threshold value, i.e:
FRDY = (Nbytes ≥ threshold)
During the inter-frame period, ‘threshold’ is forced to ‘1’ to flush the FIFO; otherwise,
‘threshold’ is determined by FHTR.
FRDY is level sensitive, i.e. it can be cleared only by reading FIFO.
Ready: This bit indicates the state of the access request between the host and the
STV0974:
0 = Register access in progress,
1 = AR, DR and DW can be accessed by the host.
For a read access, RDY is cleared upon host write to AR (MSB); it is set by the micro-
core when DR is updated with the register data.
For a write access, RDY is cleared upon host write to DW; it is set by the micro-core
when the internal register is updated.
Note: RDY is high when AR points to the interface indirect registers.
Description
Functional description
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