M5307C3 Freescale Semiconductor, M5307C3 Datasheet - Page 120

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M5307C3

Manufacturer Part Number
M5307C3
Description
KIT EVALUATION FOR MCF5307
Manufacturer
Freescale Semiconductor
Series
ColdFire®r
Type
Microprocessorr
Datasheet

Specifications of M5307C3

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MCF5307
Interface Type
Ethernet
For Use With/related Products
MCF5307
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
use in standard PCs, SDRAM devices are currently the least expensive memory available, in addition to
being one of the fastest memory types. These devices normally come packaged in handy, upgradable
modules called DIMMs, which contain several SDRAM components on one or both sides of the memory
card.
Using the SDRAM controller, the MCF5307 can seamlessly interface to standard SDRAM components and
DIMMs. Although the number of row, column, and bank select lines can vary from module to module, the
multiplexing scheme in the MCF5307 is designed to support a large variety of SDRAM configurations. To
extend this MCF5307 feature further, a PLD can be designed to interface to the MCF5307 SDRAM
controller that allows the connection of a wide variety of SDRAM DIMMs having different row and column
configurations. Thus, rather than hardwiring one specific SDRAM DIMM to a MCF5307 board design,
SDRAM DIMMs with varying row and column combinations can be swapped without re-design.
This document details a method of connecting the MCF5307 to single-sided DIMMs with 8, 9, 10, or 11
column address lines, 11, 12, or 13 row address lines, and up to 2 bank address lines using a PLD design.
This design can support up to 512 MBytes of memory, which is compatible with the MCF5307’s addressing
capability.
1.1.1 Definitions
Before the PLD design is presented, it is helpful to review some of the terminology that will be used in this
document:
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MCF5307 Memory Bank—This refers to any group of memories that are selected by one of the
MCF5307 RAS[1:0] signals. Thus, the MCF5307 can support two SDRAM banks. Note that the
RAS[1:0] signals interface to the chip-select signals (CS) on SDRAMs.
SDRAM Bank—This term is often used by SDRAM manufacturers to distinguish between the
internal partitions, or banks, in a single SDRAM device. For example, one SDRAM component can
have four internal SDRAM banks (that is, a 64-Mbit SDRAM is configured as 512K x 32 x 4 banks)
Bank selection is controlled through the bank select pins on the SDRAM.
SDRAM—Synchronous dynamic random access memory. These operate similar to asynchronous
DRAMs (ADRAMs) with the advantage of a synchronous clock, a pipelined multibank
architecture, and faster speed. These memories also maintain high memory density.
DIMM—Dual inline memory module. DIMMs contain rows of SDRAM components on one or
both sides of the memory card. This is not to be confused with the SDRAM row address lines,
called SRAS signals. Note that in this application note all DIMMs mentioned in the design will be
single-sided, since single-sided DIMMs contain two CS lines (in other words, two MCF5307
banks) that the MCF5307 can support. Double-sided DIMMs generally have four CS lines—two
on one side of the memory card and two on the other. Because double–sided modules present
greater load to the address and data lines of a processor, use of single-sided modules are preferred.
Table 1 shows a fairly complete list of the extensive DIMM configurations, along with their
associated parameters. Note that modules can have the same capacity, but have different number of
bank select lines, row and column address lines, depending on their organization.
Connecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MOTOROLA

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