M5307C3 Freescale Semiconductor, M5307C3 Datasheet - Page 126

• Manufacturer Part Number: M5307C3
• Description: KIT EVALUATION FOR MCF5307
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5307C3

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MCF5307
• Interface Type: Ethernet
• For Use With/related Products: MCF5307
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor, Inc.
1.2.2 Helper MUX Implementation
An in-system programmable device was chosen for the helper MUX implementation because it can easily
be reconfigured while on the board. The ispGAL22v10 has a 500 gate density, which easily fits the required
TM
logic for the helper MUX. Using Lattice Semiconductor’s freeware package “ispEXPERT
System Starter
Kit,” the ispGAL was programmed in ABEL-HDL. For more information on obtaining the starter kit please
refer to http://www.lattice.com/ftp/ispstarter.html.
Both the ABEL-HDL and PLD equation files for the helper MUX pictured in Figure 1 can be found at the
end of this application note in section 1.6 on page 11 and section 1.7 on page 16.
1.2.3 Helper MUX Initialization
Once implemented in a system, the helper MUX in Figure 1 can be used to interface to various 168-pin
SDRAM DIMMs by initializing the MUX select pins M[3:0] to the proper SDRAM configuration.
SDRAM configuration information can be read at boot time through a serial presence detect (SPD)
EEPROM on the SDRAM DIMM. This EEPROM contains data about the number of rows, columns, banks,
access times, etc. of the DIMM. The SPD portion of this module is accessed on pins 82 and 83 of a 168-pin
DIMM and can be connected to the SDA and SCL pins of the MCF5307, respectively. Information can be
2
read from the SPD by using these I
C pins on the MCF5307 to determine the configuration of the memory.
This information should be read at boot time and it should be used to initialize the M[3:0] lines on the helper
PLD, as well as the internal MCF5307 SDRAM configuration registers. Information on the MCF5307
SDRAM Controller initialization sequence can be found in the Motorola application note AN1766/D. The
®
specification for the Intel
PC100 can be found at http://developer.intel.com/design/chipsets/memory/
sdram.htm.
1.3 System Design
Besides interfacing the helper MUX to the MCF5307, other board design requirements must be met to allow
for the swapping of various DIMMs.
One consideration is the number of clock inputs. Some 168-pin SDRAM DIMMs only require a single clock
input on CLK0 (pin 42). Other DIMMs require two clocks on either CLK0 (pin 42) and CLK1 (pin 125) or
on CLK0 (pin 42) and CLK2 (pin 79). Yet others require four clocks; CLK0 (pin 42), CLK1 (pin 125),
CLK2 (pin 79), and CLK3 (pin 163). Thus, a clock driver with at least four outputs is recommended in the
board design to satisfy the requirements of a four-clock input DIMM. DIMMs have on-board termination
for unused clock inputs. Use of zero-delay PLL-type clock driver, such as the Cypress Semiconductor
CY2305, CY2308, or CY2309 is highly recommended.
The next consideration is the connection to the DIMM chip-select lines that control the module. For single-
sided or double-sided 168-pin DIMMs, the MCF5307 RAS0 should be connected to CS0 (pin 30) of the
module and RAS1 should be connected to CS2 (pin 45) of the module. The remaining module chip-select
lines—CS1 (pin 114) and CS3 (pin 129) should be connected to the 3.3-volt DIMM power-supply through
pull-up resistors. This ensures that chips on the back side of double-sided modules remain deselected (i.e.,
inactive) and prevents any possible contention on the data bus.
Because the back side of the DIMM is not being used in this design, its clock select line should also be
disabled. A 168-pin DIMM has two clock enable lines for each side of the DIMM, CKE0 (pin 128) and
CKE1 (pin 63), which activate a low-power/self-refresh mode of an SDRAM. It is recommended that the
CKE1 control line be left floating, while the CKE0 pin is connected to the SCKE pin of the MCF5307. The
CKE1 line controls the clock select line on the back side of DIMMs, and has a 10 K Ohm pull-up resistor
on the module itself.
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Connecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs
MOTOROLA
8
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