M5407C3 Freescale Semiconductor, M5407C3 Datasheet - Page 74

• Manufacturer Part Number: M5407C3
• Description: KIT EVAL FOR MCF5407 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5407C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5407
• Interface Type: Ethernet
• For Use With/related Products: MCF5407
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor, Inc.
The Processor and Support Logic
generate -TA internally after a preprogrammed number of wait states. In order to support
future expansion of the board, the -TA input of the processor is also connected to the
Processor Expansion Bus, J2. This allows the expansion boards to assert this line to
indicate their -TA to the processor. On the expansion boards, however, this signal should
be generated through an open collector buffer with no pull-up resistor; a pull-up resistor is
included on the board. All the -TA’s from the expansion boards should be connected to this
line.
3.1.11 Wait State Generator
The Flash ROM and SDRAM DIMM on the board may require some adjustments on the
cycle time of the processor to make them compatible with processor speed. To extend the
CPU bus cycles for the slower devices, the chip-select logic of the MCF5407 can be
programmed to generate an internal -TA after a given number of wait states. Refer to
Sections 3.1.12 and 3.1.13 for information about the wait state requirements of SDRAM
and Flash ROM respectively.
3.1.12 SDRAM DIMM
The M5407C3 has one 168-pin DIMM socket (U26) for a SDRAM DIMM. The M5407C3
will work with most PC100 SDRAM DIMMs with a few exceptions. The 5407 supports up
to two banks of SDRAM, but double-sided DIMMs require 4 bank selects to access all of
the chips. Therefore when using double-sided DIMMs only half of the available memory
will be accessible. Since DIMMs are manufactured primarily for use in PCs some DIMMs
have the DQM (byte enables) and RAS (bank selects) routed so that the DIMM cannot be
accessed as a 32-bit port.
In order to support SDRAM DIMMs with different configurations the M5407C3 uses a
helper mux (U27) to configure the address line connections to the DIMM socket. See the
Connecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs application note on the
coldfire website (www.freescale.com/coldfi re) for more information. JP21-JP24 are used
to configure the inputs to the helper mux. When dBUG comes up it will read the SDRAM
configuration information from the EEPROM on the DIMM and drive the proper
configuration data for the helper mux on PP[0:3].
If you are using a third party debugger or want to use PP[0:3] then the jumpers JP21-JP24
should be moved to the correct settings for the particular DIMM you are using. There are a
couple of ways to determine which settings should be used. First, the jumper settings for
different combinations of row and column addresses are listed in the jumper table
silkscreen on the back of the board. The settings can also be determined by allowing the
board to boot up under dBUG control. Since dBUG drives the configuration data on PP[0:3]
the data will be seen on the LEDs (D1-D4). If the LED is on then the corresponding jumper
should be OFF, and if the LED is off then the jumper should be in position 2-3.
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M5407C3 User’s Manual