HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 27

• Manufacturer Part Number: HS7750RKCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750RKCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2.8 Measurement Items
Event
Operand access count
(read/with cache)
Operand access count
(write/with cache)
Operand access count
(read and write/with cache)
Internal RAM operand
access count
All operand access count
Internal I/O area access
count
Operand cache read miss
count
Operand cache write miss
count
Operand cache read and
write miss count
Instruction cache miss
count
UTLB miss count
Instruction TLB miss count
(ITLB and UTLB misses)
Instruction cache miss
count
All instruction fetch count
Branch instruction
execution count
Branch taken count
BSR/BSRF/JSR instruction
execution count
Instruction execution count E
Keyword Description
OAR*
OAW*
OARW*
OARAM
OA
IOA
DCR
DCW
DCRW
EC
DT
ET
EF*
EA
B
BT
BBJ
The number of times the operand access is performed on
the cacheable area when the cache is enabled (read access
only).
The number of times the operand access is performed on
the cacheable area when the cache is enabled (write
access only).
The number of times the operand access is performed on
the cacheable area when the cache is enabled (both read
and write accesses).
The number of times the internal RAM area is accessed.
The number of all operand accesses.
The number of times the internal I/O area is accessed.
The number of times operand cache misses occur at data
reading.
The number of times operand cache misses occur at data
writing.
The number of times operand cache misses occur at data
reading or writing.
The number of times instruction cache misses.
The number of times UTLB misses occur at data access.
The number of times UTLB and ITLB misses occur at
instruction access.
The number of times instructions are fetched from the
cacheable area when the cache is enabled.
The number of times all instructions are fetched.
The number of times branch instructions are issued
(instructions to be counted: BF (other than displacement 0),
BF/S and BT (other than displacement 0), BT/S, BRA,
BRAF, and JMP).
The number of times branches are taken (branches to be
counted are the same as mode B).
The number of times the BSR, BSRF, or JSR instruction is
issued.
The number of times instructions are issued.
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