HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 215

• Manufacturer Part Number: HS7750RKCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750RKCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. Low-Power Modes (Sleep, Standby, and Module Standby)
Notes: 1. After the sleep mode is cleared by a break, execution restarts at the instruction
4. RESET Signals (/RESET and /MRESET)
Note: Do not start user program execution while control input signals (/RESET, /MRESET,
5. Direct Memory Access Controller (DMAC)
6. Internal I/O Registers
Note: As default, SDMR2 and SDMR3 are specified in the I/O-register definition file as the
7. Memory Access during Emulation
For low-power consumption, the SH7750R has sleep, standby, and module standby modes.
The sleep and standby modes are switched using the SLEEP instruction. When the emulator is
used, the sleep and standby modes can be cleared by either normal clearing or by the [Stop]
button. In the latter case, the user program breaks. Note, however, that if a command has
been entered in standby mode or module standby mode, a TIMEOUT error will occur.
The SH7750R RESET signals (/RESET and /MRESET) are only valid during user program
execution started with clicking the GO or STEP-type button. If these signals are input from
the user system in command input wait state, they are not sent to the SH7750R.
The DMAC operates even in the command wait state. When a data transfer request is
generated, the DMAC executes DMA transfer.
In the emulator, the internal I/O registers can be accessed from the [I/O registers] window.
However, pay attention when accessing the SDMR register of the bus-state controller. Before
accessing the SDMR register, specify addresses to be accessed in the I/O-register definition
file (SH7750R.IO) and then activate the HDI. For details on I/O-register definition files, refer
to the Hitachi Debugging Interface User's Manual.
When a memory is accessed from the memory window, etc. during user program execution,
the user program is resumed after it has stopped in the E10A emulator to access the memory.
Therefore, realtime emulation cannot be performed.
The stopping time of the user program is as follows:
2. If the memory is accessed or modified in the sleep mode, the sleep mode is cleared
3. When the SLEEP instruction is executed by STEP-type commands, set [Rate] to 6
/BREQ, and /RDY) are being low. A TIMEOUT error will occur. If the /BREQ and
/RDY signals are fixed to low during break, a TIMEOUT error will occur at memory
access.
area-2 SDMR register and area-3 SDMR register, respectively.
following the SLEEP instruction.
and execution starts at the instruction following the SLEEP instruction.
to use [Step…] from the [Run] menu. If [Rate] is 5 or less, a COMMUNICATION
TIMEOUT error occurs.
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