HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 232
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HS7750RKCI01H
Manufacturer Part Number
HS7750RKCI01H
Description
ON CHIP DEBUG EMULATOR
Manufacturer
Renesas Electronics America
Datasheets
1.HS7750RKCI01H.pdf
(264 pages)
2.HS7750RKCI01H.pdf
(38 pages)
3.HS7750RKCI01H.pdf
(9 pages)
Specifications of HS7750RKCI01H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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- Download datasheet (2Mb)
Table 6.9 Measurement Conditions (cont)
Measurement Condition Mode
Instruction execution
count
Interrupt count
UBC satisfaction count
Cache fill cycle count
Elapsed time count
Pipeline freeze cycle count PFCF
Note: The non-cache operand accesses due to the PREF instruction or TLB.c=0 do not count up.
206
UA
ECF
E
E2
EFP
ETR
INT
NMI
UB
OCF
TM
PFCD
PFB
Description
The number of times instructions are issued.
The number of times two instructions are issued at the
same time.
The number of times FPU instructions are issued.
The number of times the TRAPA instruction is executed.
The number of interrupts except NMI.
The number of NMI interrupts.
The number of times channel A of the UBC is satisfied.
The number of times channel B of the UBC is satisfied.
The number of instruction cache fill cycles.
The number of operand cache fill cycles.
The number of cycles for elapsed time.
Pipeline freeze cycle due to instruction cache misses.
Pipeline freeze cycle due to operand cache misses.
Pipeline freeze cycle due to branch instructions or
exceptions.
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