HS7750RKCI01H Renesas Electronics America, HS7750RKCI01H Datasheet - Page 259

• Manufacturer Part Number: HS7750RKCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750RKCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7.5 Performance Count Conditions (cont)
Event
Pipeline freeze cycle due
to branch instruction or
exception
Examples:
1. To set the elapsed-time measurement in the <mode> item and count using the ratio of the CPU
2. To set the elapsed-time measurement in the <mode> item, count using the ratio of the CPU
operating clock to the bus clock in the <clock> item in channel 1:
operating clock to the bus clock in the <clock> item, and set the measurement start and end at
the satisfaction of Break Condition 4 in the <range> item:
ps channel 1 mode tm clock bus (RET)
ps channel 2 mode tm clock bus range u (RET)
Count Condition
Counts only one cycle at branch instruction
execution except when the delay slot instruction is
executed with one-cycle delay. One instruction is
executed in one cycle, which is similar to the
branch count. When the instruction in the branch
destination does not exist in the instruction cache,
the delay after the second cycle is counted by the
ECF. In the PFB, all branch instructions can be
counted.
Target Mode
PFB
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