IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet

Page 1

... High-performance submicron CMOS technology • Industrial temperature range (– + available DESCRIPTION: The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improve- ments over previous SuperSync FIFOs, including the following: • ...

Page 2

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 DESCRIPTION (Continued) • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family ...

Page 3

... Initiating any operation (by activating control WEN inputs) will immediately take the device out of the power down together state. LD The IDT72255LA/72265LA are fabricated using IDT’s high on each rising speed submicron CMOS technology. PARTIAL RESET ( ) MASTER RESET ( ) LOAD ( ...

Page 4

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable ...

Page 5

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating ...

Page 6

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 ELECTRICAL CHARACTERISTICS (Commercial 10 Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time CLKL t Data Setup Time DS t Data Hold Time ...

Page 7

... When the FIFO is full, the Full Flag ( inhibiting further write operations reads are performed after a reset 8,192 writes for the IDT72255LA and 16,384 for the IDT72265LA, respectively. If the FIFO is full, the first read operation will cause HIGH. Subsequent read operations will cause go HIGH at the conditions described in Table 1 ...

Page 8

... Figure 9, 10 and 12. PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72255LA/72265LA has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the pin ...

Page 9

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 72255LA – 8,192 x 18–BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH if is LOW at Master Reset, 3FFH if is HIGH at Master Reset 17 12 FULL OFFSET REGISTER DEFAULT VALUE 07FH if is LOW at Master Reset, 3FFH if ...

Page 10

... FIFO between Reset (Master or Partial) and the time of Retransmit setup 8,192 for the IDT72255LA and D = 16,384 for the IDT72265LA. In FWFT mode 8,193 for the IDT72255LA and D= 16,385 for the IDT72265LA. If IDT Standard mode is selected, the FIFO will mark the ...

Page 11

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 change in level will only be noticeable if setup. During this period, the internal read pointer is initialized to the first location of the RAM array. EF When goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory ...

Page 12

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: MRS MRS MRS MRS MRS MASTER RESET ( ) A Master Reset is accomplished whenever the is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

Page 13

... FIFO is not full reads are performed after a reset (either MRS or SKEW (D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode) , for the relevant timing information the third valid LOW ...

Page 14

... HIGH, inhibiting further write operations reads are MRS performed after a reset (either after D writes to the FIFO (D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA) See Figure 9, Write Timing (FWFT Mode) , for the relevant timing information. IR ...

Page 15

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 FWFT FWFT/ COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE RSS t RSS t RSS t RSS t RSS t If FWFT = HIGH, RSF If FWFT = LOW, t RSF If FWFT = LOW, If FWFT = HIGH, t RSF t RSF t RSF Figure 5. Master Reset Timing ...

Page 16

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE RSS t RSS t RSS t RSS t RSF t RSF t RSF t RSF t RSF Figure 6. Partial Reset Timing t RSR t RSR If FWFT = HIGH, = HIGH If FWFT = LOW, = LOW If FWFT = LOW, = HIGH If FWFT = HIGH, ...

Page 17

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 WRITE WCLK 1 (1) t SKEW1 RCLK t t ENS ENH DATA IN OUTPUT REGISTER NOTES the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that SKEW1 If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t extra WCLK cycle ...

Page 18

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 18 ...

Page 19

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE 19 ...

Page 20

... FIFO after Master Reset more than may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, Retransmit setup procedure 8,192 for IDT72255LA and 16,384 for IDT72265LA goes HIGH RCLK cycle + t ...

Page 21

... OR 5. goes LOW RCLK cycles + t WCLK t ENS t LDS BIT 0 NOTE for the IDT72255LA and for the IDT72265LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW2 ENH t REF PAF ...

Page 22

... D = maximum FIFO depth. In IDT Standard mode 8,192 for the IDT72255LA and 16,384 for the IDT72265LA. In FWFT mode 8,193 for the IDT72255LA and 16,385 for the IDT72265LA the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that ...

Page 23

... RCLK NOTES: 1. For IDT Standard mode maximum FIFO depth 8,192 for the IDT72255LA and 16,384 for the IDT72265LA. 2. For FWFT mode maximum FIFO depth 8,193 for the IDT72255LA and 16,385 for the IDT72265LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

Page 24

... Figure 19. Block Diagram of 8,192 x 36 and 16,384 x 36 Width Expansion DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72255LA can easily be adapted to applications requiring depths greater than 8,192 and 16,384 for the IDT72265LA with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...

Page 25

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 FWFT/SI • FWFT/SI WRITE CLOCK WCLK WRITE ENABLE IDT INPUT READY 72255LA 72265LA n DATA IN Dn Figure 20. Block Diagram of 16,384 x 18 and 32,768 x 18 Depth Expansion between WCLK and transfer clock, or RCLK and transfer ...

Page 26

... IDT72255LA/72265LA SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. DATASHEET DOCUMENT HISTORY 04/19/2001 pgs and 26. ...

Page 27

... Integrated Device Technology, Inc. DIFFERENCES BETWEEN THE IDT72255LA/72265LA AND IDT72255L/72265L IDT has improved the performance of the IDT72255/72265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-for-pin compatible with the original “L” version. Some differences exist between the two versions. ...