Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 171

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 83. LIN-UART Status 0 Register – LIN Mode (UxSTAT0)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
RDA
R
7
0
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the transmit data register is empty and ready for additional data.
Writing to the transmit data register resets this bit.
0 = Do not write to the transmit data register.
1 = The transmit data register is ready to receive an additional byte to be transmitted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is
finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS signal
When this bit is read it returns the CTS signal level. If
replaced by the internal receive data Available signal to provide flow control in loopback
mode. CTS only affects transmission if the
RDA—Receive Data Available
This bit indicates that the receive data register has received data. Reading the receive data
register clears this bit.
0 = The receive data register is empty.
1 = There is a byte in the receive data register.
PLE—Physical Layer Error
This bit indicates that transmit and receive data do not match when a LIN slave or master is
transmitting. This is caused by a fault in the physical layer or multiple devices driving the
bus simultaneously. Reading the status 0 register or the receive data register clears this bit.
0 = Transmit and receive data match.
1 = Transmit and receive data do not match.
PLE
R
6
0
OE
R
5
0
P R E L I M I N A R Y
FF-E201H, FF-E211H
FE
R
4
0
CTSE
BRKD
R
3
0
bit = 1.
LBEN
TDRE
R
2
1
=
1
, the CTS input signal is
Product Specification
ZNEO
TXE
1
R
1
Z16F Series
LIN-UART
ATB
R
0
0
155