Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 222

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Operation
PS022008-0810
SDA and SCL Signals
I
2
C Interrupts
•
The I
SLAVE mode with Master arbitration. In MASTER/SLAVE mode, it is used as the only
Master on the bus or as one of several Masters on the bus with arbitration. In a multi-
Master environment, the controller switches from MASTER to SLAVE mode on losing
arbitration.
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, the SLAVE-ONLY mode is selected. In SLAVE-
ONLY mode, the device does not initiate a transaction even if software inadvertently sets
the START bit.
I
significant bit first. SCL is the clock for the I
functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The Master is responsible for driving the SCL clock signal. During the Low period of the
clock, a Slave holds the SCL signal Low to suspend the transaction if it is not ready to
proceed. The Master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the Slave releases the clock,
the I
limit to the amount of data transferred in one operation. When transmitting address, data
or acknowledge, the SDA signal changes in the middle of the Low period of SCL
receiving address, data, or acknowledge, the SDA signal is sampled in the middle of the
High period of SCL.
A low-pass digital filter is applied to the SDA and SCL receive signals by setting the filter
enable (
which is less than a system clock period in width is rejected. This filter must be enabled
when running in I
The I
request signal to the interrupt controller. If the I
interrupt is determined by bits, which are set in the I2CISTAT register. If the I
Controller is disabled, the BRG Controller is used to generate general-purpose timer
interrupts.
2
C sends all addresses, data, and acknowledge signals over the SDA line, the most-
Support for multi-master environments. If arbitration is lost when operating as a Master,
the ARBLST bit in the I2CISTAT register is set and the mode automatically switches
to Slave mode.
2
2
2
C Master continues the transaction. All data is transferred in bytes and there is no
C Controller contains multiple interrupt sources that are combined into one interrupt
C Master/Slave Controller operates in either SLAVE-ONLY mode or MASTER/
FILTEN
) bit in the I
2
C Fast mode (400 kbps) and is also used at lower data rates.
P R E L I M I N A R Y
2
C Control register. When the filter is enabled, any glitch,
2
C bus. When the SDA and SCL pin alternate
2
C Controller is enabled, the source of the
I
2
C Master/Slave Controller
Product Specification
ZNEO
Z16F Series
2
C
.
When
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