Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 172

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

®
ZNEO
Z16F Series
Product Specification
156
OE—Receive Data and Autobaud Overrun Error
This bit is set just as in normal UART operation if a receive data overrun error occurs.
This bit is also set during LIN slave autobaud if the BRG counter overflows before the end
of the autobaud sequence, indicating that the receive activity was not an autobaud character
or the master baud rate is too slow. The ATB status bit will also be set in this case. This bit
is cleared by reading the receive data register.
0 = No autobaud or data overrun error occurred.
1 = An autobaud or data overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) is detected.
Reading the receive data register clears this bit. 
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit is set in LIN mode if (a) in LinSleep state and a break of at least 4 bit times
occurred (Wake-up event) or (b) in Slave Wait Break state and a break of at least 11 bit
times occurred (Break event), or (c) in Slave Active state and a break of at least 10 bit times
occurs. Reading the status 0 register or the receive data register clears this bit.
0 = No LIN break occurred.
1 = A LIN break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the transmit data register is empty and ready for additional data.
Writing to the transmit data register resets this bit.
0 = Do not write to the transmit data register.
1 = The transmit data register is ready to receive an additional byte to be transmitted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is
finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
ATB—LIN Slave AutoBaud Complete
This bit is set in LIN SLAVE mode when an autobaud character is received. If the ABIEN
bit is set in the LIN control register then a receive interrupt is generated when this bit is set.
Reading the Status 0 register clears this bit. This bit will be 0 in LIN MASTER mode.
PS022008-0810
P R E L I M I N A R Y
LIN-UART