Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 227

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
S
Address
Figure 43. Data Transfer Format - Master Write Transaction with a 7-Bit Address
Slave
The procedure for a Master transmit operation to a 7-bit addressed Slave is given below:
1. Software initializes the MODE field in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
5. Software sets the
6. The I
7. The I
8. When one bit of address is shifted out by the SDA signal, the Transmit interrupt
9. Software responds by writing the transmit data into the I
10. The I
11. The I
12. The I
13. The I
14. If more bytes remain to be sent, return to step 9.
with either 7-bit or 10-bit slave address. The MODE field selects the address width for
this node when addressed as a Slave, not for the remote Slave. Software asserts the
IEN bit in the I
to the I
register.
asserts.
High period of SCL. The I

If the slave does not acknowledge the address byte, the I
bit in the I
I
STOP bit and clearing the TXI bit. The I
register, sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
I
sent, the Transmit interrupt asserts.
2
2
W=0
C State register. Software responds to the Not Acknowledge interrupt by setting the
C Data register.
2
2
2
2
2
2
2
C interrupt asserts, because the I
C Slave sends an acknowledge (by pulling the SDA signal Low) during the next
C Controller sends the Start condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out the SDA signal.
C Controller loads the contents of the I
C Controller shifts the data out of through the SDA signal. When the first bit is
2
C Data register.
A
2
C Interrupt Status register, sets the ACKV bit and clears the ACK bit in the
2
C Control register.
START
Data
P R E L I M I N A R Y
bit of the I
2
C Controller sets the ACK bit in the I
2
A
C Shift register with the contents of the I
2
2
C Control register.
C Control register to enable Transmit interrupts.
Data
2
C Data register is empty
2
C Controller flushes the transmit data
2
C Mode register for Master/Slave mode
2
C Shift register with the contents of the
A
2
C Slave.
2
2
C Data register.
C Controller sets the
I
Data
2
C Master/Slave Controller
Product Specification
ZNEO
2
C State register. 
A/A
Z16F Series
2
C Data
NCKI
P/S
211