Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 295

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Linked List Setup and Operation
The software initially needs to create the descriptor lists and allocate the buffers for each
list. In addition, software needs to do the following:
1. Write the
2. Set the CONTROL field in the descriptor (not the DMA) for the appropriate
3. Write the destination address to the destination field.
4. Write the source address to the source field.
5. Write the transfer length for this buffer.
6. If this descriptor has its
7. If there are additional descriptors in the list then set them up using the same procedure
After the descriptor has been set up, the software must write the DMAxLAR in the appro-
priate DMA with the address of the descriptor. The DMA performs the following:
1. Generate a request to the CPU.
2. Place the DMAxLAR address on the bus and fetch the CONTROL word from the
3. Fetch the Destination address from the descriptor and place it in the DMAxDAR
4. Fetch the Source address from the descriptor and place it in the DMAxSAR register in
5. Fetch the TXLN length from the descriptor and place it in the DMAxTXLN register in
operation:
–
–
–
–
–
–
–
–
–
–
descriptor.
listed above.
descriptor. This word is then placed in the DMAxCTL register of the DMA channel.
register in the DMA channel.
the DMA channel.
the DMA channel.
DMAxEN, set to one
LOOP, set to one to not have the descriptor modified.
TXSIZE, set the appropriate size for byte, word or quad.
DSTCTL, set this for increment, decrement, or fixed.
SRCCTL, set this for increment, decrement, or fixed.
IEOB, set to one if an interrupt must be generated when this descriptor is closed.
TXFR, set this bit if the LAR is used to point to the next descriptor.
EOF, if this is an end of frame buffer then set this bit.
HALT, if the DMA must stop at the end of this buffer then set this bit to one.
CMDSTAT, set this field with a command for the selected peripheral.
DAMxREQSEL
P R E L I M I N A R Y
TXFR
to select the appropriate request source.
bit set then the LAR address to point to the next
Product Specification
ZNEO
DMA Controller
Z16F Series
279