Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 268

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

Table 128. ADC0 MAX Register (ADC0MAX)
Table 129. ADC Timer0 Capture Register, high byte (ADCTCAP_H)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[7:4]
[3:0]
LASTCHAN0
Bit Position
[7:0]
ADC0 Max Register
ADC Timer0 Capture Register
7
7
00H–FFH
Value (H) Description
The ADC0 Max register. This register determines the highest channel that the Convert on
Read increments too.
The ADC Timer0 Capture register contains the sixteen bits of the ADC Timer0 count. The
access to the ADC Timer0 Capture register is read-only. It reads 8 bits at a time or as a 
16-bit word.
Value (H) Description
0H
0
6
6
ADC Timer0 Count High Byte
The Timer0 count is held in the data registers until the next ADC conversion is
started.
Reserved - must be 0.
LAST CHANNEL0
These bits determine the last ch annel number to increment to when the
Convert On Read is set.
Reserved
0
5
5
P R E L I M I N A R Y
4
4
ADCTCAPH
FF-E507H
FF-E512H
R/W
R
X
3
3
2
LASTCHAN0
2
Product Specification
0H
ZNEO
1
1
Analog Functions
Z16F Series
0
0
252