MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 1243

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
A.7.2.1
In
Freescale Semiconductor
Drive mode
Load capacitance C
Thresholds for delay measurement points
Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
Figure A-7
(CPOL = 1)
(CPOL = 0)
(Output)
(Output)
(Output)
(Output)
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
(Input)
MISO
MOSI
SCK
SCK
SS1
Master Mode
the timing diagram for master mode with transmission format CPHA = 0 is depicted.
LOAD
1
,
on all outputs
2
5
10
MSB IN2
MSB OUT2
Description
MC9S12XE-Family Reference Manual Rev. 1.23
6
Figure A-7. SPI Master Timing (CPHA = 0)
4
Table A-27. Measurement Conditions
1
Bit MSB-1. . . 1
4
Bit MSB-1. . . 1
9
12
12
LSB IN
LSB OUT
13
13
(20% / 80%) V
Full drive mode
Appendix A Electrical Characteristics
Value
50
11
3
DDX
Unit
pF
—
V
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