MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 317

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.2.5
Read: Only when unlocked AND not secured AND not armed AND with a TSOURCE bit set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Freescale Semiconductor
Address: 0x0024, 0x0025
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Resets
Bit[15:0]
Other
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
POR
Field
15–0
1. Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D
1. Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B
W
R
CDCM
ABCM
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
00
01
10
11
00
01
10
11
—
15
X
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the
Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when
the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace
buffer address. The same is true for word reads while the debugger is armed. The POR state is undefined Other
resets do not affect the trace buffer contents. .
Debug Trace Buffer Register (DBGTBH:DBGTBL)
—
14
X
13
—
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
X
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Figure 8-7. Debug Trace Buffer Register (DBGTB)
Match2 mapped to comparator C/D outside range....... Match3 disabled.
12
—
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
X
Match2 mapped to comparator C/D inside range....... Match3 disabled.
MC9S12XE-Family Reference Manual Rev. 1.23
Table 8-18. DBGTB Field Descriptions
11
—
X
Table 8-16. CDCM Encoding
Table 8-17. ABCM Encoding
—
10
X
—
X
9
Bit 8
—
Description
Description
X
Reserved
Reserved
8
Description
Bit 7
—
X
7
(1)
(1)
Bit 6
—
X
6
Chapter 8 S12X Debug (S12XDBGV3) Module
Bit 5
—
X
5
Bit 4
—
X
4
Bit 3
—
X
3
Bit 2
—
X
2
Bit 1
—
X
1
Bit 0
—
X
0
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