MC9S12XEP100CAG Freescale Semiconductor, MC9S12XEP100CAG Datasheet - Page 253

• Manufacturer Part Number: MC9S12XEP100CAG
• Description: IC MCU 16BIT 1M FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24-ch x 12-bit
• Cpu Family: HCS12X
• Device Core Size: 16b
• Frequency (max): 50MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 25
• Operating Supply Voltage (typ): 1.8/2.8/5V
• Operating Supply Voltage (max): 1.98/2.9/5.5V
• Operating Supply Voltage (min): 1.72/2.7/3.13V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Incl. S12X_EBI registers
2. Refer to S12X_MMC section.
3. If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4. Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
5.4.2
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see
Table
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
Freescale Semiconductor
Data direction signals
threshold enabled on
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Data select signals
(if 16-bit data bus)
address access
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Reduced input
External wait
Chip Selects
(if Enabled)
Bus signals
Properties
Flash area
5-14), internal writes on ADDRx and DATAx (see
feature
Internal Visibility
(4)
Single-Chip
Normal
Single-Chip Modes
—
—
—
—
—
—
—
Table 5-9. Summary of Functions (continued)
MC9S12XE-Family Reference Manual Rev. 1.23
Single-Chip
Special
—
—
—
—
—
—
—
Signal Properties
ADDR[22:1]
Expanded
DATA[15:0]
Table 5-4
Normal
Refer to
EWAIT
UDS
LDS
CS0
CS1
CS2
CS3
WE
RE
—
Table 5-15
ADDR[22:20]/
ADDR[19:16]/
Single-Chip
ADDR[15:0]/
IQSTAT[3:0]
DATA[15:0]
DATA[15:0]
Emulation
IVD[15:0]
ACC[2:0]
ADDR0
1 cycle
LSTRB
EWAIT
RW
Chapter 5 External Bus Interface (S12XEBIV4)
—
—
Expanded Modes
to
Table
ADDR[22:20]/
ADDR[19:16]/
5-17). RW and LSTRB
ADDR[15:0]/
IQSTAT[3:0]
DATA[15:0]
DATA[15:0]
Emulation
Expanded
IVD[15:0]
ACC[2:0]
ADDR0
LSTRB
1 cycle
EWAIT
EWAIT
CS0
CS1
CS2
CS3
RW
Table 5-12
ADDR[22:0]
DATA[15:0]
Table 5-4
Special
Refer to
ADDR0
LSTRB
1 cycle
Test
RW
—
—
to
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