ATTINY461V-10SU Atmel, ATTINY461V-10SU Datasheet - Page 160

IC MCU AVR 4K FLASH 10MHZ 20SOIC

ATTINY461V-10SU

Manufacturer Part Number
ATTINY461V-10SU
Description
IC MCU AVR 4K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY461V-10SU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire, SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
20SOIC W
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY461V-10SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATTINY461V-10SUR
Manufacturer:
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Quantity:
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15.13.3
15.13.3.1
15.13.3.2
160
ATtiny261/461/861
ADCL and ADCH – The ADC Data Register
ADLAR = 0
ADLAR = 1
Table 15-5.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
Bit
0x05 (0x25)
0x04 (0x24)
Read/Write
Initial Value
153.
ADPS2
0
1
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
15
15
R
R
R
R
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
ADPS1
R
R
R
R
6
0
0
6
0
0
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
5
0
0
5
0
0
ADC4
ADC6
12
12
R
R
R
R
4
0
0
4
0
0
ADPS0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
3
0
0
3
0
0
ADC2
ADC4
10
10
R
R
R
R
2
0
0
2
0
0
“ADC Conversion Result” on
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
1
0
0
128
16
32
64
8
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
0
0
0
2588E–AVR–08/10
ADCH
ADCL
ADCH
ADCL

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