AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 263
![IC MCU AVR32 512K FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALTTA
Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATEVK1104.pdf
(826 pages)
Specifications of AT32UC3A0512-ALTTA
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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25.7.1.1
25.7.1.2
32058J-AVR32-04/11
Clock Divider
Transmitter Clock Management
Figure 25-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register CMR, allowing a Master Clock division by up
to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is
programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Mas-
ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is even or odd.
Figure 25-5.
Table 25-2.
The transmitter clock is generated from the receiver clock or the divider clock or an external
clock scanned on the TX_CLOCK I/O pad. The transmitter clock is selected by the CKS field in
TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the
CKI bits in TCMR.
Maximum
CLK_SSC / 2
Divided Clock
Master Clock
Master Clock
Divided Clock
Divided Clock Generation
DIV = 3
DIV = 1
CLK_SSC
/ 2
Divided Clock Frequency = CLK_SSC/2
Divided Clock Frequency = CLK_SSC/6
Clock Divider
12-bit Counter
Minimum
CLK_SSC / 8190
CMR
Divided Clock
AT32UC3A
263
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