AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 395

IC MCU AVR32 512K FLASH 144LQFP

AT32UC3A0512-ALTTA

Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3A0512-ALTTA

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A0512-ALTTA
Manufacturer:
Atmel
Quantity:
10 000
27.6.7.3
Figure 27-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11).
32058J–AVR32–04/11
In te rn a lly s y n c h ro n iz e d
N W A IT s ig n a l
N B S 0 , N B S 1 ,
C L K _ S M C
A 0 , A 1
A [2 5 :2 ]
N W A IT
D [1 5 :0 ]
Ready Mode
N C S
N W E
6
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure
27-30.
4
5
4
3
3
2
1
2
E X N W _ M O D E = 1 1 (R e a d y m o d e )
W R IT E _ M O D E = 1 (N W E _ c o n tro lle d )
N W E _ P U L S E = 5
N C S _ W R _ P U L S E = 7
W rite c y c le
0
1
F R O Z E N S T A T E
0
1
Figure 27-29
0
1
0
and
AT32UC3A
Figure
27-30. After
Fig-
395

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