AT32UC3A0512-ALTTA Atmel, AT32UC3A0512-ALTTA Datasheet - Page 343

IC MCU AVR32 512K FLASH 144LQFP

AT32UC3A0512-ALTTA

Manufacturer Part Number
AT32UC3A0512-ALTTA
Description
IC MCU AVR32 512K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3A0512-ALTTA

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A0512-ALTTA
Manufacturer:
Atmel
Quantity:
10 000
26.8.3
Name:
Access Type:
Offset:
Reset Value:
• ONEBIT: Start Frame Delimiter Selector
0: Start Frame delimiter is COMMAND or DATA SYNC.
1: Start Frame delimiter is One Bit.
0:The Manchester Start bit is a 0 to 1 transition
1: The Manchester Start bit is a 1 to 0 transition.
• MAN: Manchester Encoder/Decoder Enable
0: Manchester Encoder/Decoder are disabled.
1: Manchester Encoder/Decoder are enabled.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAX_ITERATION
Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on SYNC value.
1: The sync field is updated when a character is written into THR register.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
32058J–AVR32–04/11
MODSYNC
ONEBIT
31
23
15
7
USART Mode Register
CHMODE
CHRL
: Manchester Synchronization Mode
VAR_SYNC
MODSYNC
30
22
14
MR
Read-write
0x4
-
6
DSNACK
MAN
21
13
29
5
NBSTOP
USCLKS
FILTER
INACK
28
20
12
4
OVER
27
19
11
3
CLKO
PAR
26
18
10
2
MODE
MAX_ITERATION
MODE9
25
17
9
1
AT32UC3A
SYNC/CPHA
MSBF/CPOL
24
16
8
0
343

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