HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 144

• Manufacturer Part Number: HD64F3672FPV
• Description: IC H8/3672 MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3672FPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Timer V
10.3.2
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
10.3.3
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Rev.4.00 Nov. 02, 2005 Page 118 of 304
REJ09B0143-0400
Bit Bit Name Initial Value R/W
7
6
5
4
3
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
Time Constant Registers A and B (TCORA, TCORB)
Timer Control Register V0 (TCRV0)
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Compare Match Interrupt Enable B
Compare Match Interrupt Enable A
Timer Overflow Interrupt Enable
Description
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
When this bit is set to 1, interrupt request from the OVF bit
in TCSRV is enabled.
Counter Clear 1 and 0
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.