HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 203

IC H8/3672 MCU FLASH 64LQFP

HD64F3672FPV

Manufacturer Part Number
HD64F3672FPV
Description
IC H8/3672 MCU FLASH 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets

Specifications of HD64F3672FPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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13.4
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data transfer.
13.4.1
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the
SCK3 pin, the clock frequency should be 16 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 13.3.
Clock
Serial data
Serial
data
Figure 13.3 Relationship between Output Clock and Transfer Data Phase
Operation in Asynchronous Mode
Clock
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Start
bit
1 bit
Figure 13.2 Data Format in Asynchronous Communication
LSB
0
D0
One unit of transfer data (character or frame)
D1
Transmit/receive data
D2
7 or 8 bits
D3
1 character (frame)
D4
D5
Section 13 Serial Communication Interface 3 (SCI3)
D6
MSB
D7
Rev.4.00 Nov. 02, 2005 Page 177 of 304
Parity
bit
1 bit,
or none
0/1
1
Stop bit
1 or
2 bits
1
Mark state
REJ09B0143-0400
1

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