HD64F3672FPV Renesas Electronics America, HD64F3672FPV Datasheet - Page 211
HD64F3672FPV
Manufacturer Part Number
HD64F3672FPV
Description
IC H8/3672 MCU FLASH 64LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheets
1.DF36912GFHV.pdf
(277 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.HD64F3672FXV.pdf
(334 pages)
Specifications of HD64F3672FPV
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
26
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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13.5
Figure 13.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the
SCI3, the transmitter and receiver are independent units, enabling full-duplex communication
through the use of a common clock. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
13.5.1
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of
one character, and when no transfer is performed the clock is fixed high.
13.5.2
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 13.4.
Operation in Clocked Synchronous Mode
Clock
SCI3 Initialization
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Figure 13.9 Data Format in Clocked Synchronous Communication
Don’t care
*
LSB
Bit 0
One unit of transfer data (character or frame)
Bit 1
Bit 2
Bit 3
Section 13 Serial Communication Interface 3 (SCI3)
8-bit
Bit 4
Rev.4.00 Nov. 02, 2005 Page 185 of 304
Bit 5
Bit 6
MSB
Bit 7
Don’t care
REJ09B0143-0400
*
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