MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 18

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Power, Dual-Core Microcontroller
18
SRSP1 (07h, 00h)
Initialization:
Read/Write Access:
SRSP1.[15:0]:
AD0LSB (08h, 00h)
Initialization:
Read/Write Access:
AD0LSB.[7:0]:
AD1LSB (09h, 00h)
AD2LSB (0Ah, 00h)
AD3LSB (0Bh, 00h)
AD4LSB (0Ch, 00h)
AD5LSB (0Dh, 00h)
MREQ0 (0Eh, 00h)
Initialization:
Read/Write Access:
MREQ0.[3:0]: REQCM[3:0]
MREQ0.4: RSPIE
MREQ0.5: REQCDV
MREQ0.[7:6]: Reserved
______________________________________________________________________________________
Slave Response Register 1
This register is reset to 0000h on all forms of reset.
Unrestricted read access only to the UserCore.
Unrestricted read/write access to the DSPCore.
Slave Response Register 1 Bits 15:0. These bits are used to supply output data to the master. To
notify the master that data is ready to be read, the RSPCDV bit should be set to 1 by software. The
slave should not write further data to SRSP1 until the valid condition (RSPSDV = 1) is cleared by the
master software.
Analog-to-Digital Converter 0 Least Significant Byte Output Register
This register is reset to FFh on all forms of reset.
Unrestricted read access.
Analog-to-Digital Converter 0 Least Significant Byte Output Register. This register always provides
read access to the least significant byte of the most current ADC0 data sample acquired from the
respective sinc3 filter. See the below table for the least significant byte available OSR options.
Reading from the AD0 register results in the ABF0 flag being cleared by hardware (when set)
unless the read operation is performed simultaneously with a write. What this means is that when
OSR > 32, AD0LSB should be read first if the clearing of ABF0 is intended to indicate that the full
result (AD0LSB and AD0) was read. Reading a disabled ADC returns the data last acquired if the
associated buffer full flag is set and returns FFFFh if the flag is clear.
Analog-to-Digital Converter 1 Least Significant Byte Output Register
Analog-to-Digital Converter 2 Least Significant Byte Output Register
Analog-to-Digital Converter 3 Least Significant Byte Output Register
Analog-to-Digital Converter 4 Least Significant Byte Output Register
Analog-to-Digital Converter 5 Least Significant Byte Output Register
Master Request Register 0
This register is reset to 00h on all forms of reset.
Unrestricted read/write access to the UserCore (except REQCDV; see the bit description).
Unrestricted read access only to the DSPCore (except REQCDV; see the bit description).
Request Command Bits 3:0. These bits are written by the master to supply a command request to the
slave. To notify the slave that a command is ready to be read, the REQ0DV bit should be set to 1.
Response Registers Interrupt Enable. Setting this bit to 1 enables an interrupt for the slave
response status data valid flag (which is associated with Response Registers 0 and 1). The status
data valid (interrupt) flag is reported in SRSP0.5. Clearing this bit to 0 disables the interrupt
associated with the response status data valid flag.
Request Command Data Valid Flag. This flag can only be set by the master (UserCore). This flag
should be set once a valid command is supplied in the REQCM[3:0] field of the MREQ0 and/or data
supplied in the MREQ1, MREQ2 registers to notify the slave that these registers are ready for
reading. This flag can only be cleared by slave (DSPCore) software.
Reserved. Reads return 0.
Special Function Register Bit Descriptions (continued)
OSR
128
256
32
64
ADC DATA OUTPUT WIDTH
16
19
22
24
AD0LSB FORMAT
d2–d0, 00000b
00000000b
d5–d0, 00b
d7–d0