MAXQ3108-FFN+ Maxim Integrated Products, MAXQ3108-FFN+ Datasheet - Page 31

• Manufacturer Part Number: MAXQ3108-FFN+
• Description: IC MCU DUAL-CORE 16BIT 28-TSSOP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ3108-FFN+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, JTAG, SPI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RASH (1Eh, 01h)
Initialization:
Read/Write Access:
RASH.[3:0]:
RASH.[7:4]: Reserved
RASL (1Fh, 01h)
Initialization:
Read/Write Access:
RASL.[15:0]:
T2CNA (00h, 02h)
Initialization:
Read/Write Access:
T2CNA.0: G2EN
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Low-Power, Dual-Core Microcontroller
RTC Alarm Time-of-Day High Register (8-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Bits 3:0 are write accessible when either (ADE = 0 or RTCE = 0). Bits 3:0 are read accessible at all
times. Bits 7:4 are not write accessible and always read 0.
RTC Time-of-Day High Bit 3:0. This register contains the most significant bits for the 20-bit time-of-
day alarm. The time-of-day alarm is formed by the RASH and the RASL registers and only the lower
20 bits is meaningful for the alarm function. The time-of-day alarm is triggered when 1) the
subsecond counter rolls over and 2) the 20 significant bits of the RASH:RASL register pair match
the 20 least significant bits of the RTC (the RTSH:RTSL register pair).
Reserved. Reads return 0.
RTC Alarm Time-of-Day Low Register (16-Bit Register)
This register is battery backed through POR so long as V
is indeterminate on the very first POR and must be configured initially by the user. This register is
unaffected by other resets.
Unrestricted read. Write accessible when BUSY = 0 and either (ADE = 0 or RTCE = 0).
RTC Time-of-Day Low Bit 15:0. This register contains the least significant bits for the 20-bit time-of-
day alarm. The time-of-day alarm is formed by the RASH and the RASL registers and only the lower
20 bits are meaningful for the alarm function. The time-of-day alarm is triggered when 1) the
subsecond counter rolls over and 2) the 20 significant bits of the RASH:RASL register pair match
the 20 least significant bits of the RTC (the RTSH:RTSL register pair).
Timer 2 Control Register A
This register is cleared to 00h on all forms of reset.
Unrestricted read/write.
Gating Enable. This bit enables the external T2P pin to gate the input clock to the 16-bit (T2MD =
0) or highest 8-bit (T2MD = 1) timer. Gating uses T2P as an input, thus it can only be used when
T2OE0 = 0 and C/T2 = 0. Gating is not possible on the low 8-bit timer (T2L) when timer 2 is
operated in dual 8-bit mode. Gating does not make sense when counter operation is selected as
the T2 input is being counted. The G2EN bit serves a different purpose when capture and reload
have been defined for both edges (CCF[1:0] = 11b and CPRL2 = 1). For this special case, setting
G2EN = 1 allows the T2POL0 bit to specify which edge does not cause a reload. If T2POL0 is 0,
there is no reload on the falling edge; if T2POL0 is 1, there is no reload on the rising edge.
0 = gating disabled
1 = gating enabled
Special Function Register Bit Descriptions (continued)
BAT(MIN)
BAT(MIN)
< V
< V
BAT
BAT
< V
< V
BAT(MAX)
BAT(MAX)
; however, it
; however, it
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