ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 32

• Manufacturer Part Number: ATMEGA163-8AI
• Description: IC AVR MCU 16K A/D 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Timer/Counter Interrupt
Flag Register – TIFR
32
ATmega163(L)
(at vector $00A) is executed if a capture triggering event occurs on PD6 (ICP), i.e., when
the ICF1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare A Match Interrupt is enabled. The corresponding interrupt (at
vector $00C) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare B Match Interrupt is enabled. The corresponding interrupt (at
vector $00E) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when the
OCF1B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$010) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and always reads as zero.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$012) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 7 – OCF2: Output Compare Flag2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2
and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when
executing the corresponding Interrupt Handling Vector. Alternatively, OCF2 is cleared
by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare Match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2
Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding inteRrupt Handling Vector. Alterna-
tively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and
TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the
Bit
$38 ($58)
Read/Write
Initial Value
OCF2
R/W
7
0
TOV2
R/W
6
0
ICF1
R/W
5
0
OCF1A
R/W
4
0
OCF1B
R/W
3
0
TOV1
R/W
2
0
R
1
–
x
TOV0
R/W
1142E–AVR–02/03
0
0
TIFR