ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 47

• Manufacturer Part Number: ATMEGA163-8AI
• Description: IC AVR MCU 16K A/D 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TCNT1 Timer/Counter1 Write
TCNT1 Timer/Counter1 Read
Timer/Counter1 Output
Compare Register – OCR1AH
and OCR1AL
Timer/Counter1 Output
Compare Register – OCR1BH
and OCR1BL
1142E–AVR–02/03
When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP
Register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined
with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1
Timer/Counter1 Register simultaneously. Consequently, the high byte TCNT1H must be
accessed first for a full 16-bit register write operation.
When the CPU reads the low byte TCNT1L, the data of the Low Byte TCNT1L is sent to
the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register. When
the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the
TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a full
16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
The Output Compare Registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status Register. A software write to the Timer/Counter
Register blocks compare matches in the next Timer/Counter clock cycle. This prevents
immediate interrupts when initializing the Timer/Counter.
A Compare Match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a
temporary register TEMP is used when OCR1A/B are written to ensure that both bytes
are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH,
the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte,
OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
Bit
$2B ($4B)
$2A ($4A)
Read/Write
Initial Value
Bit
$29 ($49)
$28 ($48)
Read/Write
Initial Value
MSB
MSB
R/W
R/W
R/W
R/W
15
15
7
0
0
7
0
0
R/W
R/W
R/W
R/W
14
14
6
0
0
6
0
0
R/W
R/W
R/W
R/W
13
13
5
0
0
5
0
0
R/W
R/W
R/W
R/W
12
12
4
0
0
4
0
0
R/W
R/W
R/W
R/W
11
11
3
0
0
3
0
0
R/W
R/W
R/W
R/W
10
10
2
0
0
2
0
0
ATmega163(L)
R/W
R/W
R/W
R/W
9
1
0
0
9
1
0
0
LSB
R/W
R/W
LSB
R/W
R/W
8
0
0
0
8
0
0
0
OCR1AH
OCR1BH
OCR1AL
OCR1BL
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