ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 78

• Manufacturer Part Number: ATMEGA163-8AI
• Description: IC AVR MCU 16K A/D 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART Baud Rate Registers –
UBRR and UBRRHI
Double Speed
Transmission
The Baud Rate Generator in
Double UART Speed Mode
78
ATmega163(L)
This is a 12-bit register which contains the UART Baud Rate according to the equation
on the previous page. The UBRRHI contains the four most significant bits, and the
UBRR contains the eight least significant bits of the UART Baud Rate.
The ATmega163 provides a separate UART mode which allows the user to double the
communication speed. By setting the U2X bit in the UART Control and Status Register
UCSRA, the UART speed will be doubled. Note, however, that the receiver will in this
case only use half the number of samples (only 8 instead of 16) for data sampling and
clock recovery, and therefore requires more accurate baud rate setting and system
clock.
The data reception will differ slightly from Normal mode. Since the speed is doubled, the
Receiver front-end logic samples the signals on RXD pin at a frequency eight times the
baud rate. While the line is idle, one single sample of logical zero will be interpreted as
the falling edge of a start bit, and the start bit detection sequence is initiated. Let sample
1 denote the first zero-sample. Following the 1 to 0-transition, the Receiver samples the
RXD pin at samples 4, 5, and 6. If two or more of these three samples are found to be
logical ones, the start bit is rejected as a noise spike and the receiver starts looking for
the next 1 to 0-transition.
If however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 4, 5, and 6. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift Register as they are sampled. Sampling of an incoming character is
shown in Figure 48.
Figure 48. Sampling Received Data When the Transmission Speed is Doubled
RECEIVER
SAMPLING
Note that the baud-rate equation is different from the equation on page 78 when the
UART speed is doubled:
•
•
•
•
For standard crystal frequencies, the most commonly used baud rates can be generated
by using the UBR settings in Table 28. UBR values which yield an actual baud rate dif-
fering less than 1.5% from the target baud rate, are bold in the table. However, since the
Bit
$20 ($40)
$09 ($29)
Read/Write
Initial Value
RXD
BAUD = Baud Rate
f
UBR = Contents of the UBRRHI and UBRR Registers, (0 - 4095)
Note that this equation is only valid when the UART Transmission Speed is doubled.
CK
= Crystal Clock frequency
START BIT
MSB
R/W
15
R
–
7
0
0
D0
R/W
14
R
–
6
0
0
D1
R/W
13
–
5
R
0
0
BAUD
D2
R/W
12
R
=
–
4
0
0
----------------------------- -
8(UBR
D3
f
MSB
R/W
R/W
CK
11
3
0
0
+
D4
1
R/W
R/W
10
2
0
0
D5
R/W
R/W
9
1
0
0
D6
LSB
LSB
R/W
R/W
8
0
0
0
1142E–AVR–02/03
D7
UBRRHI
UBRR
STOP BIT