ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 352

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
MAILBOX DATA LENGTH CONTROL REGIS-
TER (MDLC)
All bits of this register is write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: xxxx xxxx (xxh)
Bit 7 = TGT Transmit Global Time
This bit is active only when the hardware is in the
Time Trigger Communication mode, TTCM bit of
the CCR register is set.
0: MTSRH and MTSRL registers are not sent.
1: MTSRH and MTSRL registers are sent in the
6:4 = Reserved. Forced to 0 by hardware.
Bit 3:0 = DLC[3:0] Data Length Code
This field defines the number of data bytes a data
frame contains or a remote frame request.
MAILBOX DATA REGISTERS (MDAR[7:0])
All bits of this register are write protected when the
mailbox is not in empty state.
Read / Write
Reset Value: xxxx xxxx (xxh)
Bit 7:0 = DATA[7:0] Data
A data byte of the message. A message can con-
tain from 0 to 8 data bytes.
352/429
9
DATA7
TGT
last two data bytes of the message.
7
7
DATA6
0
DATA5
0
DATA4
0
DATA3
DLC3
DATA2
DLC2
DATA1
DLC1
DATA0
DLC0
0
0
MAILBOX TIME STAMP LOW REGISTER
(MTSLR)
Read / Write
Reset Value: xxxx xxxx (xxh)
Bit 7:0 = TIME[7:0] Message Time Stamp Low
This fields contains the low byte of the 16-bit timer
value captured at the SOF detection.
MAILBOX TIME STAMP HIGH REGISTER
(MTSHR)
Read / Write
Reset Value: xxxx xxxx (xxh)
Bit 7:0 = TIME[15:8] Message Time Stamp High
This field contains the high byte of the 16-bit timer
value captured at the SOF detection.
TIME15 TIME14 TIME13 TIME12 TIME11 TIME10
TIME7
7
7
TIME6
TIME5
TIME4
TIME3
TIME2
TIME1
TIME9
TIME0
TIME8
0
0