ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 362

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
10.11.1 Main Characteristics
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10.11.2 Introduction
The Analog to Digital Converter (ADC) consists of
an input multiplex channel selector feeding a suc-
cessive approximation converter.
Figure 155. ADC Block Diagram
362/429
EXTERNAL
INTERNAL
TRIGGER
(from MFT0)
9
TRIGGER
(EXTRG)
10-bit Resolution
Monotonicity: Guaranteed
No missing codes: Guaranteed
3-bit INTCLK/2 Frequency Prescaler
Internal/External Trigger availability
Continuous/Single Modes
Autoscan Mode
Power Down Mode
16 10-bit data registers (two per channel)
Two analog watchdogs selectable on adjacent
channels
CONTROL REG.2
(CLR2)
(CLR1)
CONTROL REG.1
CONTROL
LOGIC
DATA REGISTER H/L13
DATA REGISTER H/L12
DATA REGISTER H/L11
DATA REGISTER H/L10
DATA REGISTER H/L 8
DATA REGISTER H/L 5
DATA REGISTER H/L 4
DATA REGISTER H/L 3
DATA REGISTER H/L 2
DATA REGISTER H/L 0
DATA REGISTER H/L15
DATA REGISTER H/L14
DATA REGISTER H/L 9
DATA REGISTER H/L 7
DATA REGISTER H/L 6
DATA REGISTER H/L 1
COMPARE LOGIC
INTERRUPT UNIT
AUTOSCAN LOGIC
The conversion time depends on the INTCLK fre-
quency and the prescaler factor stored in the
PR[2:0] bits of the CLR2 register (R253-page 63)).
AV
ence voltage pins. Up to 16 multiplexed Analog In-
puts are available depending on the specific de-
vice type. With the AUTOSCAN feature, a group of
signals can be converted sequentially by simply
programming the starting address of the first ana-
log channel to be converted.
There are two Analog Watchdogs used for the
continuous hardware monitoring of two consecu-
tive input channels selectable by means of the
CC[3:0] bits in the CLR1 register (R252-page 63).
An Interrupt request is generated whenever the
converted value of either of these two analog in-
puts exceeds the upper or lower programmed
threshold values.
DD
10 bit
CONVERSION
and AV
RESULT
ANALOG TO DIGITAL
APPROXIMATION
SUCCESSIVE
COMPARE RESULT REGISTER
CONVERTER
THRESHOLD H/L REGISTER BU
THRESHOLD H/L REGISTER BL
THRESHOLD H/L REGISTER AH
THRESHOLD H/L REGISTER AL
SS
INT. CONTROL REGISTER
INT. VECTOR POINTER
CK PRESCALER
are the high and low level refer-
DIVIDER by 2
CKAD
INTCLK
ANALOG
MUX
ANALOG
SECTION
AIN 15
AIN 14
AIN 13
AIN 12
AIN 11
AIN 10
AIN 9
AIN 8
AIN 7
AIN 6
AIN 5
AIN 4
AIN 3
AIN 2
AIN 1
AIN 0