MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 11

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure
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20-4
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20-24
21-1
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21-8
22-1
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23-1
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23-6
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23-11
Freescale Semiconductor
Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination ................................................. 20-9
Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination................ 20-9
Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination .............. 20-10
Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................ 20-10
Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination ................ 20-11
Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ................ 20-11
Longword Read; EBI=11; 32-Bit Port; Internal Termination................................................ 20-12
Word Write; EBI=11; 16/32-Bit Port; Internal Termination .................................................. 20-13
Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination................................. 20-14
Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination ................ 20-14
Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination................................... 20-15
Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination .................. 20-15
Longword Read with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-16
Longword Write with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-17
Example of a Misaligned Longword Transfer...................................................................... 20-18
Example of a Misaligned Word Transfer ............................................................................. 20-18
Longword Write Access To 32-Bit Port Terminated with TEA Timing................................. 20-20
Master Reset Timing ........................................................................................................... 20-22
Normal Reset Timing .......................................................................................................... 20-23
Software Watchdog Timer Reset Timing ............................................................................ 20-24
Soft Reset Timing ............................................................................................................... 20-25
Test Access Port Block Diagram........................................................................................... 21-2
TAP Controller State Machine............................................................................................... 21-3
Output Cell (O.Cell) (BC–1) .................................................................................................. 21-4
Input Cell (I.Cell). Observe only (BC–4)................................................................................ 21-5
Output Control Cell (En.Cell) (BC–4) .................................................................................... 21-5
Bidirectional Cell (IO.Cell) (BC–6)......................................................................................... 21-6
General Arrangement for Bidirectional Pins.......................................................................... 21-6
Bypass Register .................................................................................................................... 21-8
MCF5272 Pinout (196 MAPBGA) ......................................................................................... 22-1
196 MAPBGA Package Dimensions (Case No. 1128A-01) .................................................. 22-2
Clock Input Timing Diagram.................................................................................................. 23-5
General Input Timing Requirements ..................................................................................... 23-7
Read/Write SRAM Bus Timing.............................................................................................. 23-9
SRAM Bus Cycle Terminated by TA ................................................................................... 23-10
SRAM Bus Cycle Terminated by TEA................................................................................. 23-11
Reset and Mode Select/HIZ Configuration Timing.............................................................. 23-12
Real-Time Trace AC Timing................................................................................................ 23-13
BDM Serial Port AC Timing................................................................................................. 23-13
SDRAM Signal Timing ........................................................................................................ 23-15
SDRAM Self-Refresh Cycle Timing .................................................................................... 23-16
MII Receive Signal Timing Diagram.................................................................................... 23-17
MCF5272 ColdFire
List of Figures (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
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