MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 447

IC MPU 66MHZ COLDFIRE 196-MAPBGA

MCF5272VM66

Manufacturer Part Number
MCF5272VM66
Description
IC MPU 66MHZ COLDFIRE 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5272VM66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Cpu Speed
66MHz
Embedded Interface Type
UART, QSPI, USB, TDM
Digital Ic Case Style
BGA
No. Of Pins
196
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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19.17.9 Debug Data (DDATA[3:0])
Debug data signals (DDATA[3:0]) display captured processor data and breakpoint status.
19.17.10 Device Test Enable (TEST)
TEST is used to put the device into various manufacturing test modes. It should be tied to VDD for normal
operation.
19.18 Operating Mode Configuration Pins
The MCF5272 has four mode-select signals, some of which are shared with output signals used during
normal device operation. These signals are HI-Z, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and
QSPI_CS0/BUSW0. BYPASS is a Freescale test mode signal and should never have a pull-down resistor.
The remaining three mode-select signals must each have a 4.7-K¾ pull-up or pull-down resistor. These
signals are sampled on the rising edge of Reset Output (RSTO).
Freescale Semiconductor
MCF5272 ColdFire
1
PST[3:0]
1100
1101
1110
1111
These encodings are asserted for multiple cycles.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1
1
1
1
Table 19-7. Processor Status Encoding
Continue execution
Begin execution of PULSE instruction or WDDATA.
Begin execution of PULSE instruction
Begin execution of taken branch
Reserved
Begin execution of RTE instruction
Begin 1 byte transfer on DDATA
Begin 2 byte transfer on DDATA
Begin 3 byte transfer on DDATA
Begin 4 byte transfer on DDATA
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for an interrupt
Processor is halted
Begin execution of an instruction
Entry into user mode
®
Integrated Microprocessor User’s Manual, Rev. 3
Definition
Signal Descriptions
19-37

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