MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 124

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Debug Support
These registers are accessed through the BDM port by new BDM commands,
described in
that specifies the register, as shown in
5-6
0x0A–0x0B
0x01–0x05
DRc[4–0]
0x0C
0x0D
0x0E
0x00
0x06
0x07
0x08
0x09
0x0F
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
31
31
31
31
31
31
All debug control registers are writable from the external development system or the CPU via the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read or written through the BDM port using the
RDMREG
Section 5.5.3.3, “Command Set
Configuration/status register
Reserved
Address attribute trigger register
Trigger definition register
Program counter breakpoint register
Program counter breakpoint mask register
Reserved
Address breakpoint high register
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written
through the BDM port using the
and
MCF5272 ColdFire
WDMREG
15
15
15
15
15
15
commands
Register Name
Figure 5-4. Debug Programming Model
Table 5-3. BDM/Breakpoint Registers
®
Table
.
Integrated Microprocessor User’s Manual, Rev. 3
7
5-3.
Descriptions.” These commands contain a 5-bit field, DRc,
RDMREG
NOTE
0
0
0
0
0
0
ABLR
ABHR
CSR
DBR
DBMR
PBR
PBMR
TDR
AATR
and
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Configuration/status register
Data breakpoint register
Data breakpoint mask register
PC breakpoint register
PC breakpoint mask register
Trigger definition register
WDMREG
Abbreviation
DBMR
PBMR
ABHR
AATR
ABLR
CSR
DBR
TDR
PBR
—
—
commands.
WDMREG
0x0000_0000
0x0000_0005
0x0000_0000
Initial State
—
—
—
—
—
—
—
—
Freescale Semiconductor
and
RDMREG
p. 5-10
p. 5-14
p. 5-13
p. 5-13
p. 5-12
p. 5-12
p. 5-7
p. 5-9
p. 5-9
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