MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 201

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

In
In
CLT = 1.
Freescale Semiconductor
Table
Table
9-11, the timing configuration is RTP = 61, RC = negligible, RCD = 1, RP = 1, and CLT = 1.
9-12, the timing configuration is RTP = 61, RC = negligible, RCD = 0 (or 1), RP = 1 (or 0), and
Table 9-11. SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port
Single-beat read
Single-beat
longword read
Single-beat write
Single-beat
longword write
Burst read
Burst write
Single-beat read
Single-beat longword read
Single-beat write
Single-beat longword write Page miss 6-1
Burst read
Burst write
Table 9-12. SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1)
MCF5272 ColdFire
SDRAM Access
SDRAM Access
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
Page miss
Page hit
®
Integrated Microprocessor User’s Manual, Rev. 3
Page miss 8
Page hit
Page miss 8-1
Page hit
Page miss 6
Page hit
Page hit
Page miss 8-1-1-1-1-1-1-1 = 15 9-1-1-1-1-1-1-1 = 16
Page hit
Page miss 6-1-1-1-1-1-1-1 = 13 6-1-1-1-1-1-1-1 = 13
Page hit
or (RCD=1, RP = 0)
9
5
9-1
5-1
7
3
7-1
3-1
9-1-1-1-1-1-1-1 = 16
5-1-1-1-1-1-1-1 = 12
7-1-1-1-1-1-1-1 = 14
3-1-1-1-1-1-1-1 = 10
REG = 0, INV = 0
5
5-1
3
3-1
5-1-1-1-1-1-1-1 = 12 6-1-1-1-1-1-1-1 = 13
3-1-1-1-1-1-1-1 = 10 3-1-1-1-1-1-1-1 = 10
REG = 0, INV = 0
Number of System Clock Cycles
Number of System Clock Cycles
10
6
10-1
6-1
7
3
7-1
3-1
10-1-1-1-1-1-1-1 = 17
6-1-1-1-1-1-1-1 = 13
7-1-1-1-1-1-1-1 = 14
3-1-1-1-1-1-1-1 = 10
9
6
9-1
6-1
6
3
6-1
3-1
REG = 1, INV = 0
REG = 1, INV = 0
SDRAM Controller
9-11