MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 344

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
14.4.1.2
Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.
The user normally writes 1 word into this segment for each queue command to be executed. The user
cannot read transmit RAM.
Out-bound data must be written to transmit RAM in a right-justified format. The unused bits are ignored.
The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most
significant bit first and remains in transmit RAM until overwritten by the user.
14.4.1.3
The CPU writes one byte of control information to this segment for each QSPI command to be executed.
Command RAM is write-only memory from a user’s perspective.
Command RAM consists of 16 bytes with each byte divided into two fields. The peripheral chip select
field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer
options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in
QWR[NEWQP] through the address in QWR[ENDQP].
The QSPI executes a queue of commands defined by the control bits in each command RAM entry which
sequence the following actions:
Before any data transfers begin, control data must be written to the command RAM, and any out-bound
data must be written to transmit RAM. Also, the queue pointers must be initialized to the first and last
entries in the command queue.
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are
controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is
used to drive outgoing data and to latch incoming data.
14.4.2
The maximum QSPI clock frequency is one-fourth the clock frequency applied at the CLKIN pin. Baud
rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the
QSPI_CLK rate from the system clock, CLKIN, divided by two.
A baud rate value of zero turns off the QSPI_CLK. The desired QSPI_CLK baud rate is related to CLKIN
and QMR[BAUD] by the following expression:
QMR[BAUD] = CLKIN / [2 × (desired QSPI_CLK baud rate)]
14-6
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•
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chip-select pins are activated
data is transmitted from transmit RAM and received into the receive RAM
the synchronous transfer clock QSPI_CLK is generated
Baud Rate Selection
Transmit RAM
Command RAM
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor