MCIMX357DVM5B Freescale Semiconductor, MCIMX357DVM5B Datasheet - Page 31

• Manufacturer Part Number: MCIMX357DVM5B
• Description: PROCESSOR MULTIMEDIA 400PBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357DVM5B

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 400-BGA
• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 400
• Operating Temperature Range: -20°C To +70°C
• Processor Type: I.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

4.9.3
There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these
PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via
EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to
EXTAL24M, bypassing the internal oscillator.
DPLL specifications are listed in
1
4.9.4
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point
access (TPA) that supports TRACECLK frequencies up to 133 MHz.
Figure 9
Freescale Semiconductor
Reference clock frequency
Max. allowed reference clock phase noise
Frequency lock time (FOL mode or non-integer MF)
Phase lock time
Max. allowed PL voltage ripple
There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.
CS10
CS11
ID
depicts the TRACECLK timings of ETM, and
MISO hold time
SPI_RDY setup time
DPLL Electrical Specifications
Embedded Trace Macrocell (ETM) Electrical Specifications
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Parameter
Table 26. CSPI Interface Timing Parameters (continued)
Parameter
Figure 9. ETM TRACECLK Timing Diagram
Table
Table 27. DPLL Specifications
27.
Min. Typ. Max.
10
—
—
—
—
Table 28
24
—
—
—
—
Symbol
t
t
0.03
0.01
0.15
Hmiso
SDRY
100
100
150
100
150
80
lists the timing parameters.
2 Tdck
MHz
Unit
mV
μs
μs
1
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
Fmodulation < 50 kHz
50 kHz < Fmodulation 300 Hz
Fmodulation > 300 KHz
Min.
5
5
Comments
Max.
—
—
—
—
Units
ns
ns
31