MCIMX357DVM5B Freescale Semiconductor, MCIMX357DVM5B Datasheet - Page 63

• Manufacturer Part Number: MCIMX357DVM5B
• Description: PROCESSOR MULTIMEDIA 400PBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357DVM5B

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 400-BGA
• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 400
• Operating Temperature Range: -20°C To +70°C
• Processor Type: I.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Figure 42
4.9.8.5
Serial management channel timing is accomplished using FEC_MDIO and FEC_MDC. The FEC
functions correctly with a maximum MDC frequency of 2.5 MHz.
channel timings.
The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII
specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Freescale Semiconductor
Num
M10
M11
M12
M13
M14
M15
shows MII asynchronous input timings listed in
FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
FEC_MDIO (input) to FEC_MDC rising edge setup
FEC_MDIO (input) to FEC_MDC rising edge hold
FEC_MDC pulse width high
FEC_MDC pulse width low
FEC_CRS, FEC_COL
MII Serial Management Channel Timing
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Figure 42. MII Asynch Inputs Timing Diagram
Characteristic
Table 48. MII Transmit Signal Timing
Table
M9
47.
Table 48
Min.
40%
40%
—
18
0
0
lists MII serial management
Max.
60%
60%
—
—
—
5
FEC_MDC period
FEC_MDC period
Units
ns
ns
ns
ns
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