CLRC63201T/0FE,112 NXP Semiconductors, CLRC63201T/0FE,112 Datasheet - Page 20

• Manufacturer Part Number: CLRC63201T/0FE,112
• Description: IC I.CODE HS READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: I-Coder

Specifications of CLRC63201T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693, ISO18000-3
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2199-5; 935269690112; CLRC632; CLRC63201TD

NXP Semiconductors
CLRC632_35
Product data sheet
PUBLIC
9.3.3 FIFO buffer status information
9.3.4 FIFO buffer registers and flags
9.4 Interrupt request system
The microprocessor can get the following FIFO buffer status data:
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The CLRC632 can generate an interrupt signal when:
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by
Table 18
Table 19.
The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
HiAlert
LoAlert
Flags
FIFOLength[6:0]
FIFOOvfl
FlushFIFO
HiAlert
HiAlertIEn
HiAlertIRq
LoAlert
LoAlertIEn
LoAlertIRq
WaterLevel[5:0]
•
•
•
•
•
•
the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
the FIFO buffer full warning: bit HiAlert
the FIFO buffer empty warning: bit LoAlert
the FIFO buffer overflow warning: bit FIFOOvfl.
bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
=
shows the related FIFO buffer flags in alphabetic order.
=
Associated FIFO buffer registers and flags
FIFOLength WaterLevel
64 FIFOLength
–
Rev. 3.5 — 10 November 2009
Register name
FIFOLength
ErrorFlag
Control
PrimaryStatus
InterruptEn
InterruptRq
PrimaryStatus
InterruptEn
InterruptRq
FIFOLevel
Multiple protocol contactless reader IC (MIFARE/I-CODE1)
073935
WaterLevel
Bit
6 to 0
4
0
1
1
1
0
0
0
5 to 0
51) and activating pin IRQ. The signal
Equation
Equation
1:
Register address
04h
0Ah
09h
03h
06h
07h
03h
06h
07h
29h
CLRC632
© NXP B.V. 2009. All rights reserved.
2:
20 of 126
(1)
(2)