CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 26

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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again until programming is completed and the status bit is re-
set to 0.
The device hardware internally generates the voltages and
timing signals necessary for programming. No additional
power supply is required, nor any software required except to
check the status bit for completion of programming. The min-
imum time required to erase and reprogram a byte or word is
1.1 ms. The programmed values can be verified by using nor-
mal memory read operations. The prescaler output drives a
10-bit counter to generate timing pulses and there are five re-
load registers to produce various pulse widths.
If a reset occurs during a programming or erase operation,
the operation is terminated. The reset is extended until the
flash memory returns to the idle state. Therefore, the timing
logic and program or erase state machine is not cleared on
reset; they are cleared on power-up with the clear signal ac-
tive until the bus signals are in a known state.
The flash EEPROM data memory does not have permanent
read-protection or write-protection features like those avail-
able for the EEPROM program memory. However, the Data
Memory Write Key Register provides a way to “lock” the data
written to the data memory.
9.3.3
The DMCSR register is a byte-wide, read/write register used
with the flash EEPROM data memory or ISP flash EEPROM
program memory. When writing to this register, all reserved
bits must be written with 0 for the memory to operate proper-
ly. There are two status/control bits, as shown in the register
format below.
ZEROWS
DMBUSY
ERASE
Upon reset, the DMCSR register is cleared to zero when the
flash memory on the chip is in the idle state.
9.3.4
The DMPSLR register is a byte-wide, read/write register that
selects the prescaler divider ratio for the EEPROM data
memory programming clock. Before you write to the data
7
Reserved
6
5
Data Memory Control and Status Register
(DMCSR)
Data Memory Prescaler Register (DMPSLR)
4
Zero Wait-State Access. When cleared (0), the
flash EEPROM data memory will be read in two
cycles. When set (1), the flash EEPROM data
memory will be read in one cycle.
Data Memory Busy. This bit is automatically set
to 1 when the flash EEPROM data memory or
the ISP flash EEPROM program memory is
busy being programmed, and cleared to 0 at all
other times. (The MSTAT.PGMBUSY is also set
to 1 whenever the DMBUSY bit is set to 1.)
Erase ISP Flash Program Memory Page.
When set (1) a valid write to the ISP flash EE-
PROM program memory will erase the entire
ISP flash EEPROM program memory page
pointed to by the write address rather than per-
forming a write to the addressed memory loca-
tion. This bit should be cleared to 0 and remain
cleared after the write operation.
ERASE
3
DMBUSY
2
ZEROWS
1
Reserved
0
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memory for the first time, you should program the DMPSLR
register with the proper prescaler value, an 8-bit value called
FTDIV. The device divides the system clock by (FTDIV+1) to
produce the data memory programming clock.
You should choose a value of FTDIV to produce a clock of the
highest possible frequency that is equal to or just less than
200 kHz. Upon reset, this register is programmed by default
with the value 63 hex (99 decimal), which is an appropriate
setting for a 20 MHz system clock.
9.3.5
The DMSTART register is a byte-wide read/write register that
controls the program/erase start delay time. This value is
loaded into the lower 8 bits of the flash timing counter, and at
the same time, 00
write to the data memory for the first time, you should pro-
gram the DMSTART register with the proper prescaler value,
an 8-bit value called FTSTART. The flash timing counter gen-
erates a delay of (FTSTART + 1) prescaler output clocks. The
default value provides a delay time of 10 s when the prescal-
er output clock is 200kHz. Do not modify this register while
program/erase operation is in progress.
Upon reset, this register resets to 01
ory on the chip is in idle state.
9.3.6
The DMTRAN register is a byte-wide read/write register that
controls some program/erase transition times. This value is
loaded into the lower 8 bits of the flash timing counter, and at
the same time, 00
write to the data memory for the first time, you should pro-
gram the DMTRAN register with the proper prescaler value,
an 8-bit value called FTTRAN. The flash timing counter gen-
erates a delay of (FTTRAN + 1) prescaler output clocks. The
default value provides a delay time of 5 s when the prescaler
output clock is 200kHz. Do not modify this register while pro-
gram/erase operation is in progress.
Upon reset, this register resets to 00
ory on the chip is in idle state.
9.3.7
The DMPROG register is a byte-wide read/write register that
controls the programming pulse width. This value is loaded
into the lower 8 bits of the flash timing counter, and at the
same time, 00
write to the data memory for the first time, you should pro-
gram the DMPROG register with the proper prescaler value,
an 8-bit value called FTPROG. The flash timing counter gen-
erates a programming pulse width of (FTPROG + 1) prescal-
er output clocks. The default value provides a delay time of
30 s when the prescaler output clock is 200kHz. Do not mod-
ify this register while program/erase operation is in progress.
Upon reset, this register resets to 05
ory on the chip is in idle state.
Data Memory Start Time Reload Register
(DMSTART)
Data Memory Transition Time Reload Register
(DMTRAN)
Data Memory Programming Time Reload
Register (DMPROG)
2
is loaded into the upper 2 bits. Before you
2
2
is loaded into the upper 2 bits. Before you
is loaded into the upper 2 bits. Before you
16
1 6
1 6
when the flash mem-
when the flash mem-
when the flash mem-