CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 43

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The register format is shown below.
13.3
The Wake-Up Interrupt Control Register 1 (WKICTL1) regis-
ter is a word-wide read/write register that selects the interrupt
request signal for the associated channels WUI0 to WUI7.
Upon reset, WKICTL1 is set to 0, which selects MIWU Inter-
rupt Request 0 for all eight channels. The register format is
shown below.
WKINTR0:7 Wake-Up Interrupt Request Select. Each field
13.4
The Wake-Up Interrupt Control Register 2 (WKICTL2) regis-
ter is a word-wide read/write register that selects the interrupt
request signal for the associated channels WUI8 to WUI15.
Upon reset, WKICTL2 is set to 0, which selects MIWU Inter-
rupt Request 0 for all eight channels. The register format is
shown below.
WKINTR8:5 Wake-Up Interrupt Request Select. Each field
15
WKINTR
15
WKINTR
15
15
7
00
01
10
11
14 13
14 13
WKINTR
WKINTR
WAKE-UP INTERRUPT CONTROL
REGISTER 1 (WKCTL1)
WAKE-UP INTERRUPT CONTROL
REGISTER 1 (WKCTL2)
14
6
WUI15
WUI0
12 11
12 11
selects which of the following four interrupt re-
quests outputs to the ICU31L are to be activat-
ed for the corresponding channel.
selects which of the following four interrupt re-
WKINTR
enables MIWU Interrupt Request 0
enables MIWU Interrupt Request 1
enables MIWU Interrupt Request 2
enables MIWU Interrupt Request 3
WKINTR
13
5
10
10
WKEN15-WKEN0
WKINTR
WKINTR
9
9
WKEDG
12
4
8
8
WKINTR
WKINTR
7
7
11
3
Figure 9. Multi-Input Wake-Up Module Block Diagram
6
6
5
WKINTR
5
WKINTR
10
2
4 3
4 3
WKPND
WKINTR
WKINTR
15
0
1
9
2
2
WKINTR
WKINTR
1
1
15
0
8
0
0
0
Peripheral Bus
. . . . . . . . . .
43
WKENA
13.5
The Wake-Up Pending (WKPND) register is a word-wide
read/write register in which the Multi-Input Wake-Up module
latches any detected trigger conditions. Register bits 0
through 15 serve as latches for channels WUI0 through
WUI15, respectively. A bit cleared to 0 indicates that no trig-
ger condition has occurred. A bit set to 1 indicates that a trig-
ger condition has occurred and is pending on the
corresponding channel. This register is cleared upon reset.
The CPU can only write a 1 to any bit position in this register.
If the CPU attempts to write a 0, it has no effect on that bit.
To clear a bit in this register, the CPU must use the WKPCL
register (described below). This implementation prevents a
potential hardware-software conflict during a read-modify-
write operation on the WKPND register.
The register format is shown below.
13.6
The Wake-Up Pending Clear (WKPCL) register is a word-
wide write-only register that lets the CPU clear bits in the WK-
PND register. Writing a 1 to a bit position in the WKPCL reg-
ister clears the corresponding bit in the WKPND register.
Writing a 0 leaves the corresponding bit in the WKPND reg-
ister unchanged.
Reading this register location returns unknown data. There-
fore, do not use a read-modify-write sequence to set the in-
dividual bits. In other words, do not attempt to read the
15
00
01
10
11
WAKE-UP PENDING REGISTER (WKPND)
WAKE-UP PENDING CLEAR REGISTER
(WKPCL)
0
quests outputs to the ICU31L are to be activat-
ed for the corresponding channel.
enables MIWU Interrupt Request 0
enables MIWU Interrupt Request 1
enables MIWU Interrupt Request 2
enables MIWU Interrupt Request 3
WKICTL1-2
WKPD15-WKPD0
4
EXINT3:0 to ICU
Wake-Up Signal
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