CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 32

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
Each entry in the Dispatch Table consists of two bytes that
provide bits 1 through 16 of the starting address of the corre-
sponding service routine. The full 21-bit address of a service
routine is reconstructed by adding a leading 0 and a trailing
0 to the 16-bit table entry.
The INTBASE register is a pointer to the Dispatch Table.
Upon reset, the initialization software must write the starting
address of the Dispatch Table to the INTBASE register, a 21-
bit register with the five most significant bits and the least sig-
nificant bit always equal to 0. It is typically kept in the flash
EEPROM program memory. The Dispatch Table is 48 words
long.
Each interrupt or trap source has an associated vector num-
ber ranging from 0 to 31, as indicated in Table10. When an
interrupt occurs, the hardware multiplies the vector by 2,
adds the result to the contents of the INTBASE register, and
uses the resulting address to obtain the service routine start-
ing address from the corresponding entry in the Dispatch Ta-
ble. This address is placed in the Program Counter so that
the CPU begins executing the interrupt service routine.
Figure5 summarizes the method used by the device to gen-
erate the starting address of a service routine.
10.1.3
When an interrupt occurs, the CPU automatically preserves
the contents of the Program Counter (PC) and Processor
Status Register (PSR) by pushing them on the interrupt stack
and decrementing the Interrupt Stack Pointer by four. The
service routine ends with a Return from Exception (RETX) in-
struction, which returns control to the interrupted program by
restoring the PC and PSR values and incrementing the Inter-
rupt Stack Pointer (ISP) by four.
Prior to using any interrupts, the Interrupt Stack Pointer (ISP)
must be initialized so that it points to a space in RAM where
the interrupt stack will be kept. The stack grows downward in
memory (toward address zero) when an interrupt occurs and
items are pushed onto the stack. The stack shrinks upward
in memory when an interrupt service routine ends and items
are popped from the stack.
Many routines need to use the general-purpose registers R0
through R13. To preserve the existing register contents, a
routine can save register contents on the program stack upon
start of the routine and restore the register contents prior to
completion of the routine. The software can also use the pro-
gram stack to transfer data parameters from one routine to
38: INT22 (Reserved)
39: INT23 (VTUD Interrupt Request 4)
40: INT24 (VTUD Interrupt Request 3)
41: INT25 (VTUD Interrupt Request 3)
42: INT26 (VTUD Interrupt Request 1)
43: INT27 (T2B Timer 2 Interrupt B)
44: INT28 (T2A Timer 2 Interrupt A)
45: INT29 (T1B Timer 1Interrupt B)
46: INT30 (T1A Timer 1Interrupt A)
47: INT31 (RTI Timer 0)
Stack Usage
Table 10 Dispatch Table Entries
32
another when the parameters are too large to easily fit into
the registers. A high-level language typically allocates the lo-
cal (non-static) variables on the stack.
The pointer to the program stack is the SP register, which
must be initialized prior to any register save/restore opera-
tions or data transfer operations. Using the program stack, an
interrupt routine needs to initially save the contests of all reg-
isters that it uses, and restore those register contents before
returning to the interrupted program.
10.2
A non-maskable interrupt is triggered by a falling edge on the
NMI input pin, which generates a software trap. The NMI pin
is an asynchronous input with Schmitt trigger characteristics
and an internal synchronization circuit. Therefore, no exter-
nal synchronizing is needed.
Upon reset, the non-maskable interrupt is disabled and
should remain disabled until the software initializes the inter-
rupt table, interrupt base, and interrupt stack pointer. It can
be enabled by setting either of two control bits in the External
NMI Control/Status (EXNMI) register. The two bits are called
the EN (Enable) bit and the ENLCK (Enable and Lock) bit.
The EN bit enables the NMI trap until an NMI trap event or a
reset occurs. An NMI trap automatically resets the EN bit. Us-
ing this bit to enable the NMI trap is intended for applications
where the NMI pin is toggled frequently but nested NMI traps
are not needed. The trap service routine should re-enable the
NMI trap by setting the EN bit before returning to the main
program.
The ENLCK bit enables the NMI trap and locks it in the en-
abled state. In other words, it leaves the NMI trap enabled
even after the trap occurs. It can be cleared only by a reset
operation. After the bit is set, an NMI trap is triggered by each
falling edge on the NMI pin, allowing nested NMI traps.
To use the EN bit, the ENLCK must remain cleared to 0. Oth-
erwise, the EN bit is ignored.
10.3
Maskable interrupts can be enabled or disabled under soft-
ware control. There are 31 level-triggered maskable interrupt
sources (including some reserved for future expansion), or-
ganized into levels of priority. If more than one interrupt event
occurs at any given time, the interrupt source with the highest
priority is serviced first. The others must wait until the high-
est-priority interrupt is serviced and is no longer pending.
Figure11 lists the maskable interrupt sources of the device
in order of priority, from the highest-priority interrupt (IRQ31)
to the lowest (IRQ0).
To enable a maskable interrupt, the enable bit must be set in
the applicable peripheral module and also in the appropriate
Interrupt and Enable Mask register, IENAM0 or IENAM1. In
addition, both the Global Maskable Interrupt Enable bit (I)
and the Local Maskable Interrupt Enable bit (E) must be set
to 1 in the PSR register. If either one of these bits is 0, then
all maskable interrupts are disabled. The CR16B core sup-
ports IRQ0, but ICU31L reserves IRQ0 so that it is not con-
nected to any interrupt source.
NON-MASKABLE INTERRUPT
MASKABLE INTERRUPTS