CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 27

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.3.8
The DMERASE register is a byte-wide read/write register
that controls the erase pulse width. This value is loaded into
the upper 8 bits of the flash timing counter, and at the same
time, 11
the data memory for the first time, you should program the
DMERASE register with the proper prescaler value, an 8-bit
value called FTER. The flash timing counter generates a
erase pulse width of 4 (FTER + 1) prescaler output clocks.
The default value provides a delay time of 1ms when the
prescaler output clock is 200kHz. Do not modify this register
while program/erase operation is in progress.
Upon reset, this register resets to 31
ory on the chip is in idle state.
For mass erase, this value should be changed to C7
the flash EEPROM data memory goes to idle mode.
9.3.9
The DMEND register is a byte-wide read/write register that
controls the delay time after a program/erase operation. This
value is loaded into the lower 8 bits of the flash timing
counter, and at the same time, 00
bits. Before you write to the data memory for the first time,
you should program the DMEND register with the proper
prescaler value, an 8-bit value called FTEND. The flash tim-
ing counter generates a delay of (FTEND + 1) prescaler out-
put clocks. The default value provides a delay time of 5 s
when the prescaler output clock is 200kHz. Do not modify
this register while program/erase operation is in progress.
Upon reset, this register resets to 00
ory on the chip is in idle state.
For mass erase, this value should be changed to 13
9.3.10
The DMPCNT register is a byte-wide read-only register that
returns the value of the data memory prescaler counter.
FPCNT is the flash timing prescaler present count value.
9.3.11
The DMCNT register is a word-wide read-only register that
returns the data memory timing counter value. The reserved
bits return 000000
FTCNT[0:9] is the flash timer present count value.
9.3.12
The DMKEY register is a byte-wide, read/write register that
provides a way to “lock” the data contained in the EEPROM
data memory. Upon reset, the register is automatically set to
C9 hex, which is the key value. Writing to the EEPROM data
memory is allowed as long as the DMKEY register contains
this value. When the register contains any value other than
C9 hex, writing the EEPROM data memory is disallowed.
To “lock” the current data stored in the data memory, write an-
other value (such as 00 hex) to the DMKEY register. To “un-
lock” the data memory, write the value C9 hex to the DMKEY
register.
2
Data Memory Erase Time Reload Register
(DMERASE)
Data Memory End Time Reload Register
(DMEND)
Data Memory Prescaler Count Register
(DMPCNT)
Data Memory Timer Count Register (DMCNT)
Data Memory Write Key Register (DMKEY)
is loaded into the lower 2 bits. Before you write to
2
.
2
is loaded into the upper 2
1 6
16
when the flash mem-
when the flash mem-
16
1 6
.
when
27
Note:
PGMKEY register used with the program memory. It is not
necessary to write the key value to DMKEY every time you
write to the data memory.
9.4
The In-System Program memory is part of the flash memory
array that contains the flash EEPROM data memory. It is not
possible to access the ISP memory while programming the
flash EEPROM data memory or access the flash EEPROM
data memory while programming the ISP memory. The 1.5K
bytes of ISP memory resides in the address range of E000-
E5FF and is used for storing the boot ROM. The ROM con-
tains the code that performs in-system programming, and is
programmed at the factory. In ISP mode, code execution
starts at address E000.
The ISP program memory and flash EEPROM data memory
share the same memory array, which makes it impossible to
access one type of memory while the other is being pro-
grammed.
The ISP memory has the following features:
9.4.1
The ISP flash EEPROM program memory read accesses
can operate without wait cycles with a CPU clock rate of up
to 20MHz in the normal mode. At higher clock rates, read ac-
cesses can operate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by BIU Configuration (BCFG) register and
the Static Zone 1 Configuration (SZCFG1) register. These
registers are described in Section8.0.
9.4.2
All program and erase operations must be preceded by writ-
ing the proper key to the program memory key register ISP-
KEY. The programming code can be in-system RAM, but
cannot be from ISP flash EEPROM program memory or flash
EEPROM data memory as accesses within these ranges are
— 1.5K bytes flash EEPROM program memory
— Page size of 4 words, divided into two rows of 2 words
— Odd and even bytes within a page can be erased sep-
— 30 s programming pulse width per word
— Page mode erase with 1ms pulse, mass erase with
— All erased memory bits read 1
— Fast read access time
— Requires valid key for program and erase to proceed
— Provide memory protection and security features for
— Security features may limit accesses to ISP memory
— Disable memory when address is out of range to pre-
— Mass erase only allowed in test modes
— Provide busy status during programming and erase
— Read/write accesses disabled during programming/
— Programming high voltage and timing generated on-
each
arately
4ms pulse
flash EEPROM program memory
vent accessing data memory
erase
chip
Operation of this register is different in from the
Reading
User-Coded Programming Routines
ISP MEMORY
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